公开(公告)号：US07091598B2

公开(公告)日：2006-08-15

申请号：US10466300

申请日：2001-01-19

申请人： Ryo Fujita ,  Osamu Kubo ,  Kouki Noguchi ,  Masaharu Kubo ,  Michihiro Mishima ,  Yasuhiko Takahashi

发明人： Ryo Fujita ,  Osamu Kubo ,  Kouki Noguchi ,  Masaharu Kubo ,  Michihiro Mishima ,  Yasuhiko Takahashi

IPC分类号： H01L23/52

CPC分类号： G06F11/261 ,  G06F11/267 ,  G06F15/7867 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/13091 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/0401

摘要： An electronic circuit device has a high-density mount board, on which are disposed a microcomputer, a random access memory, a programmable device which is a variable logic circuit represented by FPGA, and an electrically-rewritable nonvolatile memory which can store the operation program of the microcomputer. The high-density mount board has external mounting pins on the bottom surface so as to be mounted on a mother board in the same manner as a system on-chip multi-chip module. With an intended logic function being set on the programmable device, a hardware-based function to be realized by the electronic circuit device is simulated. With an operation program being written to the nonvolatile memory, a software-based function to be realized is simulated. Consequently, the device facilitates the debugging at early stages of system development, configures a prototype system, and contributes to the time reduction throughout the system development, prototype fabrication and large-scale production.

摘要翻译： 电子电路装置具有高密度安装板，微型计算机，随机存取存储器，作为由FPGA表示的可变逻辑电路的可编程装置以及可存储操作程序的电可重写非易失性存储器 的微机。 高密度安装板在底面上具有外部安装销，以与系统片上多芯片模块相同的方式安装在母板上。 通过在可编程器件上设置预期的逻辑功能，模拟由电子电路器件实现的基于硬件的功能。 通过将操作程序写入到非易失性存储器中，模拟要实现的基于软件的功能。 因此，该设备便于系统开发初期的调试，配置原型系统，有助于整个系统开发，原型制作和大规模生产的时间缩短。

公开(公告)号：US07068253B2

公开(公告)日：2006-06-27

申请号：US09891677

申请日：2001-06-25

申请人： Yasuyuki Kudo ,  Tsutomu Furuhashi ,  Yoshikazu Yokota ,  Toshimitsu Matsudo ,  Atsuhiro Higa

发明人： Yasuyuki Kudo ,  Tsutomu Furuhashi ,  Yoshikazu Yokota ,  Toshimitsu Matsudo ,  Atsuhiro Higa

IPC分类号： G09G3/36 ,  G09G5/02 ,  G09G5/00

CPC分类号： G09G3/3696 ,  G09G3/2014 ,  G09G3/2022 ,  G09G3/3611 ,  G09G2330/021

摘要： The present invention provides a liquid crystal display controller device and method which provides for a full and/or partial display with good display quality and/or low power consumption based on the scanning period for an active scan line being dependent upon a number of reference clock pulses. Some embodiments of the present invention include one or more of the following features: keeping the frequency substantially constant for different numbers of active scan lines, allowing change of the frequency due to characteristics of the LCD, displaying gradation with near linear effective voltage characteristics, displaying graduation data with lower power, or displaying a partial or full screen in a mobile device, for example, a cell phone.

公开(公告)号：US07005705B2

公开(公告)日：2006-02-28

申请号：US10261665

申请日：2002-10-02

申请人： Shigenobu Maeda ,  Takuji Matsumoto ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

发明人： Shigenobu Maeda ,  Takuji Matsumoto ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC分类号： H01L29/78

CPC分类号： H01L29/66772 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/42384 ,  H01L29/7841 ,  H01L29/78615 ,  H01L29/78654 ,  Y10S438/981

摘要： It is an object to provide an SOI device capable of carrying out body fixation and implementing a quick and stable operation. A gate insulating film (11) having a thickness of 1 to 5 nm is provided between a portion other than a gate contact pad (GP) of a gate electrode (12) and an SOI layer (3), and a gate insulating film (110) having a thickness of 5 to 15 nm is provided between the gate contact pad (GP) and the SOI layer (3). The gate insulating film (11) and the gate insulating film (110) are provided continuously.

公开(公告)号：US20050233714A1

公开(公告)日：2005-10-20

申请号：US11149546

申请日：2005-06-10

申请人： Hisayoshi Kajiwara ,  Kenji Toyota ,  Kazuhiko Hikasa ,  Taizo Yamawaki

发明人： Hisayoshi Kajiwara ,  Kenji Toyota ,  Kazuhiko Hikasa ,  Taizo Yamawaki

IPC分类号： H03G1/00 ,  H03G3/30 ,  H04B1/04 ,  H01Q11/12 ,  H03F3/45

CPC分类号： H03G3/3042 ,  H03G1/0052

摘要： A variable gain amplifier of low amplitude distortion, and low noise, having a large variable range, is provided. A variable gain differential amplifier that controls a gain by use of bias current is used as each of unit amplifiers (VGAs) making up the variable gain amplifier. A large variable gain range is obtained by series-connecting a plurality of the variable gain differential amplifiers. An attenuator is installed on the input side of the unit amplifier (VGA) at least in the initial stage. By doing so, it becomes possible to prevent amplitude distortion from occurring to the respective VGAs. An attenuator utilizing voltage division by capacitors, generating no noise, is used for lowering noise. Further, the variable gain amplifier is provided with a fixed gain amplifier installed in the final stage as necessary in order to obtain a total gain as desired. With the use of the variable gain amplifier as a variable gain amplifier for output power control of a polar loop transmitter, an excellent function for output power control can be achieved without causing significant deterioration in distortion characteristic and noise characteristic thereof.

公开(公告)号：US20050232059A1

公开(公告)日：2005-10-20

申请号：US11152526

申请日：2005-06-13

申请人： Seiji Miura ,  Kazushige Ayukawa

发明人： Seiji Miura ,  Kazushige Ayukawa

IPC分类号： G06F12/16 ,  G06F3/06 ,  G06F12/00 ,  G06F12/06 ,  G11C5/02 ,  G11C8/00 ,  G11C11/00 ,  G11C11/401 ,  G11C11/406 ,  G11C11/407 ,  G11C11/412 ,  G11C16/02 ,  G11C16/04 ,  G11C16/10 ,  G11C16/32

CPC分类号： G06F12/0246 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C11/005 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40607 ,  G11C11/412 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C29/70

摘要： A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data.

公开(公告)号：US20050190612A1

公开(公告)日：2005-09-01

申请号：US11117479

申请日：2005-04-29

申请人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Takeshi Sakata ,  Takao Watanabe

发明人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Takeshi Sakata ,  Takao Watanabe

IPC分类号： G11C5/00 ,  H03K19/0185

CPC分类号： H03K19/0016 ,  H03K19/018521

摘要： A semiconductor device including a level converter (LSC) is disclosed. The level converter comprises a voltage-up circuit (LSC1) that operates on low voltage of power supply (VDD) and steps up voltage enough to drive the level converter and a level converter circuit (LSC2) that operates on high voltage of power supply (VDDQ). The voltage-up circuit is capable of constantly generating 2×VDD so that the level converter can convert a low voltage of power supply (VDD) below 1 V to VDDQ. This voltage-up circuit can be configured only with MOSFET transistors produced by thin oxide film deposition, thus enabling high-speed operation. To facilitate designing a circuit for preventing a leakage current from occurring in the level converter during sleep mode of a low-voltage-driven circuit (CB1), the level converter circuit (LSC2) includes a leak protection circuit (LPC) that exerts autonomous control for leak prevention, dispensing with external control signals.

摘要翻译： 公开了一种包括电平转换器（LSC）的半导体器件。 电平转换器包括在低电压（VDD）下工作并升压足以驱动电平转换器的升压电路（LSC 1）和在高电压功率下工作的电平转换器电路（LSC 2） 电源（VDDQ）。 升压电路能够持续产生2xVDD，因此电平转换器可将低于1 V的低电压电压（VDD）转换为VDDQ。 该升压电路只能由通过薄氧化膜沉积制造的MOSFET晶体管配置，从而实现高速操作。 为了便于设计用于防止低电压驱动电路（CB 1）的睡眠模式期间在电平转换器中发生漏电流的电路，电平转换器电路（LSC 2）包括泄漏保护电路（LPC） 自动控制防泄漏，外接控制信号。

公开(公告)号：US06934918B2

公开(公告)日：2005-08-23

申请号：US10441221

申请日：2003-05-20

申请人： Takeshi Hashizume ,  Kumiko Tsujihashi

发明人： Takeshi Hashizume ,  Kumiko Tsujihashi

IPC分类号： G06F17/50 ,  H01L21/02 ,  H01L21/82 ,  H04L29/06 ,  H04L29/08

CPC分类号： H04L67/34 ,  H04L29/06 ,  H04L69/329

摘要： An IP generating system includes an IP (Intellectual Property) providing apparatus and at least one development apparatus. The IP providing apparatus searches for a development apparatus installing a memory compiler to be revised with reference to applied condition data managed by a master database, and transmits the revision information as to the memory compiler to the development apparatus. The system can revise the memory compiler without requiring a user to make a decision as to the necessity of the revision of the memory compiler.

摘要翻译： IP生成系统包括IP（知识产权）提供装置和至少一个开发装置。 IP提供装置参照由主数据库管理的应用条件数据来搜索安装要修改的存储器编译器的开发装置，并将该存储器编译器的修订信息发送给开发装置。 该系统可以修改存储器编译器，而不需要用户作出关于修改存储器编译器的必要性的决定。

公开(公告)号：US06933765B2

公开(公告)日：2005-08-23

申请号：US10149189

申请日：2000-12-21

申请人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Takeshi Sakata ,  Takao Watanabe

发明人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Takeshi Sakata ,  Takao Watanabe

IPC分类号： G11C5/00 ,  H03K19/0185 ,  H03L5/00

CPC分类号： H03K19/0016 ,  H03K19/018521

摘要： A semiconductor device including a level converter (LSC) is disclosed. The level converter comprises a voltage-up circuit (LSC1) that operates on low voltage of power supply (VDD) and steps up voltage enough to drive the level converter and a level converter circuit (LSC2) that operates on high voltage of power supply (VDDQ). The voltage-up circuit is capable of constantly generating 2×VDD so that the level converter can convert a low voltage of power supply (VDD) below 1 V to VDDQ. This voltage-up circuit can be configured only with MOSFET transistors produced by thin oxide film deposition, thus enabling high-speed operation. To facilitate designing a circuit for preventing a leakage current from occurring in the level converter during sleep mode of a low-voltage-driven circuit (CB1), the level converter circuit (LSC2) includes a leak protection circuit (LPC) that exerts autonomous control for leak prevention, dispensing with external control signals.

公开(公告)号：US06917552B2

公开(公告)日：2005-07-12

申请号：US10671464

申请日：2003-09-29

申请人： Riichiro Takemura ,  Tomonori Sekiguchi ,  Takeshi Sakata

发明人： Riichiro Takemura ,  Tomonori Sekiguchi ,  Takeshi Sakata

IPC分类号： G11C7/00 ,  G11C7/06 ,  G11C11/4091 ,  G11C11/4097

CPC分类号： G11C7/062 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/4097

摘要： Disclosed is a sense amplifier arrangement that achieves high-speed access and shorter cycle time when array voltage is lowered in a DRAM. In a TG clocking sense system to separate data lines between the array side and the sense amplifier side in an early stage of a sensing period, a restore amplifier RAP is added, which amplifies data lines on the array side by referring to the data in the sense amplifier, and the restore amplifier is driven by a voltage VDH higher than the array voltage VDL. As a result, high-speed sense operation of the TG clocking system is made compatible with high-speed restore operation of overdrive system, and it is possible to achieve high-speed access operation and shorter cycle time.

公开(公告)号：US06907585B2

公开(公告)日：2005-06-14

申请号：US10410283

申请日：2003-04-10

申请人： Ichiro Kohno

发明人： Ichiro Kohno

IPC分类号： G01R31/28 ,  G01R31/3183 ,  G01R31/3185 ,  G06F11/22 ,  G06F17/50 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H03K5/135 ,  H03K19/00 ,  H03K19/173

CPC分类号： G01R31/318552 ,  G01R31/318594

摘要： A method and device are provided for applying logic BIST at speed for large-scale and high-performance logic circuits without increasing test time, and decreasing test costs as a result. In one example, a logic BIST controller is divided into two portions. A clock signal having a small delay is used to drive a partial circuit that supplies a user circuit with a scan enable signal and a clock signal. A clock signal having a large delay is used to drive a partial circuit that supplies the user circuit with a test pattern and collects a test result.

摘要翻译： 提供了一种方法和装置，用于在不增加测试时间的情况下以高速逻辑BIST应用大规模和高性能逻辑电路，并降低测试成本。 在一个示例中，逻辑BIST控制器被分成两部分。 使用具有小延迟的时钟信号来驱动向用户电路提供扫描使能信号和时钟信号的部分电路。 使用具有大延迟的时钟信号来驱动向用户电路提供测试图案的部分电路并且收集测试结果。