公开(公告)号：US07215024B2

公开(公告)日：2007-05-08

申请号：US10936922

申请日：2004-09-08

Applicant: Jing-Cheng Lin ,  Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Mong-Song Liang

Inventor： Jing-Cheng Lin ,  Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Mong-Song Liang

IPC: H01L23/48

CPC classification number: H01L21/76843 ,  H01L21/32051 ,  H01L21/32136 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76877 ,  H01L21/76888 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A new method is provided for the creation of a barrier-free copper interconnect. A dual damascene structure is created in a layer of dielectric, a thin metal barrier layer is deposited. The metal barrier layer is oxidized, two layers are then deposited with the first layer comprising doped copper and the second layer comprising pure copper. The dual damascene structure is filled with copper, a thermal anneal is applied, stabilizing the deposited copper filling the dual damascene structure and forming metal oxide of the doped minority element. Excess copper is then removed from the dielectric.

Abstract translation: 提供了一种创建无障碍铜互连的新方法。 在电介质层中形成双镶嵌结构，沉积薄金属阻挡层。 金属阻挡层被氧化，然后沉积两层，第一层包含掺杂的铜，第二层包含纯铜。 双镶嵌结构填充铜，进行热退火，稳定沉积的铜填充双镶嵌结构并形成掺杂少数元素的金属氧化物。 然后从电介质中除去过量的铜。

公开(公告)号：US07030023B2

公开(公告)日：2006-04-18

申请号：US10655972

申请日：2003-09-04

Applicant: Shing-Chyang Pan ,  Ching-Hua Hsieh ,  Jing-Cheng Lin ,  Hsien-Ming Lee ,  Cheng-Lin Huang ,  Shau-Lin Shue

Inventor： Shing-Chyang Pan ,  Ching-Hua Hsieh ,  Jing-Cheng Lin ,  Hsien-Ming Lee ,  Cheng-Lin Huang ,  Shau-Lin Shue

IPC: H01L21/302

CPC classification number: H01L21/3105 ,  H01L21/28556 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76873

Abstract: A method for forming a copper damascene feature including providing a semiconductor process wafer including at least one via opening formed to extend through a thickness of at least one dielectric insulating layer and an overlying trench line opening encompassing the at least one via opening to form a dual damascene opening; etching through an etch stop layer at the at least one via opening bottom portion to expose an underlying copper area; carrying out a sub-atmospheric DEGAS process with simultaneous heating of the process wafer in a hydrogen containing ambient; carrying out an in-situ sputter-clean process; and, forming a barrier layer in-situ to line the dual damascene opening.

Abstract translation: 一种用于形成铜镶嵌特征的方法，包括提供半导体工艺晶片，其包括形成为延伸穿过至少一个介电绝缘层的厚度的至少一个通孔开口，以及覆盖所述至少一个通孔开口的上覆沟槽开口，以形成双重 大马士革开幕 在所述至少一个通孔开口底部处蚀刻通过蚀刻停止层以暴露下面的铜区域; 在含氢环境中同时加热工艺晶片，进行亚低温DEGAS工艺; 进行原位溅射清洗过程; 并且原位形成阻挡层以使双镶嵌开口成线。

公开(公告)号：US06967155B2

公开(公告)日：2005-11-22

申请号：US10618536

申请日：2003-07-11

Applicant: Jing Cheng Lin ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Mong-Song Liang

Inventor： Jing Cheng Lin ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Mong-Song Liang

IPC: H01L21/44 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/532 ,  H01L33/00

CPC classification number: H01L21/76843 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76855 ,  H01L21/76864 ,  H01L21/76873 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A new method and structure is provided for the creation of a copper dual damascene interconnect. A dual damascene structure is created in the layer of dielectric, optionally a metal barrier layer is deposited over exposed surfaces of the dual damascene structure. A copper seed layer is deposited, the dual damascene structure is filled with copper. An anneal is applied to the created copper interconnect after which excess copper is removed from the dielectric. Of critical importance to the invention, a thin layer of oxide is then deposited as a cap layer over the copper dual damascene interconnect, an etch stop layer is then deposited over the thin layer of oxide for continued upper-level metallization.

公开(公告)号：US06943111B2

公开(公告)日：2005-09-13

申请号：US10361732

申请日：2003-02-10

Applicant: Jing-Cheng Lin ,  Cheng-Lin Huang ,  Winston Shue ,  Mong-Song Liang

Inventor： Jing-Cheng Lin ,  Cheng-Lin Huang ,  Winston Shue ,  Mong-Song Liang

IPC: H01L21/768 ,  H01L21/4763 ,  H01L21/302 ,  H01L21/44

CPC classification number: H01L21/76843 ,  H01L21/76855 ,  H01L21/76864 ,  H01L21/76873 ,  H01L2221/1089

Abstract: A new method is provided for the creation of a copper seed interface capability. A first seed layer of copper alloy and a second seed layer of copper is provided over an opening in a layer of dielectric. The opening is filled with copper, the first and second seed layers are annealed.

Abstract translation: 提供了一种用于创建铜种子界面能力的新方法。 在介电层中的开口上方设置有铜合金的第一籽晶层和铜的第二晶种层。 开口填充有铜，第一和第二种子层被退火。

公开(公告)号：US20050189075A1

公开(公告)日：2005-09-01

申请号：US10789660

申请日：2004-02-27

Applicant: Shing-Chyang Pan ,  Jing-Cheng Lin ,  Hsien-Ming Lee ,  Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Chao-Hsien Peng ,  Li-Lin Su ,  Shau-Lin Shue

Inventor： Shing-Chyang Pan ,  Jing-Cheng Lin ,  Hsien-Ming Lee ,  Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Chao-Hsien Peng ,  Li-Lin Su ,  Shau-Lin Shue

IPC: B08B7/00 ,  H01J37/32 ,  H01L21/00 ,  C23F1/00

CPC classification number: H01L21/67109 ,  B08B7/0071 ,  H01J37/32862

Abstract: A reactive pre-clean chamber that contains a wafer heating apparatus, such as a high-temperature electrostatic chuck (HTESC), for directly heating a wafer supported on the apparatus during a pre-cleaning process. The wafer heating apparatus is capable of heating the wafer to the optimum temperatures required for a hydrogen plasma reactive pre-clean (RPC) process. Furthermore, degassing and pre-cleaning can be carried out in the same pre-clean chamber. The invention further includes a method of pre-cleaning a wafer using a pre-clean chamber that contains a wafer heating apparatus.

Abstract translation: 一种反应性预清洁室，其包含诸如高温静电卡盘（HTESC）的晶片加热装置，用于在预清洁过程期间直接加热支撑在装置上的晶片。 晶片加热装置能够将晶片加热到氢等离子体反应性预清洁（RPC）工艺所需的最佳温度。 此外，脱气和预清洁可以在相同的预清洁室中进行。 本发明还包括使用包含晶片加热装置的预清洁室预清洁晶片的方法。

公开(公告)号：US20050023686A1

公开(公告)日：2005-02-03

申请号：US10918816

申请日：2004-08-13

Applicant: Jing-Cheng Lin

Inventor： Jing-Cheng Lin

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/76846 ,  H01L21/76856 ,  H01L21/76873 ,  H01L2924/0002 ,  H01L2924/00

Abstract: It is a general object of the present invention to provide an improved method of fabrication in the formation of an improved copper metal diffusion barrier layer having the structure, W/WSiN/WN, in single and dual damascene interconnect trench/contact via processing with 0.10 micron nodes for MOSFET and CMOS applications. The diffusion barrier is formed by depositing a tungsten nitride bottom layer, followed by an in situ SiH4/NH3 or SiH4/H2 soak forming a WSiN layer, and depositing a final top layer of tungsten. This invention is used to manufacture reliable metal interconnects and contact vias in the fabrication of MOSFET and CMOS devices for both logic and memory applications and the copper diffusion barrier formed, W/WSiN/WN, passes a stringent barrier thermal reliability test at 400° C. Pure single barrier layers, i.e., single layer WN, exhibit copper punch through or copper spiking during the stringent barrier thermal reliability test at 400° C.

Abstract translation: 本发明的一般目的是提供一种改进的制造方法，该方法是在单和双镶嵌互连沟槽/接触通孔加工中具有以下结构的W / WSiN / WN结构的改进的铜金属扩散阻挡层的形成 微米节点用于MOSFET和CMOS应用。 扩散阻挡层通过沉积氮化钨底层，随后形成SiH4 / NH3或SiH4 / H2浸泡形成WSiN层，并沉积钨的最终顶层形成。 本发明用于在逻辑和存储器应用的MOSFET和CMOS器件的制造中制造可靠的金属互连和接触孔，并且形成的铜扩散阻挡层W / WSiN / WN在400℃下通过严格的阻挡热可靠性测试 在400℃的严格的阻隔热可靠性试验期间，纯单层阻挡层，即单层WN，表现出铜冲穿或铜尖峰。

公开(公告)号：US06797608B1

公开(公告)日：2004-09-28

申请号：US09587465

申请日：2000-06-05

Applicant: Jing-Cheng Lin

Inventor： Jing-Cheng Lin

IPC: H01L214763

CPC classification number: H01L21/76846 ,  H01L21/76856 ,  H01L21/76873 ,  H01L2924/0002 ,  H01L2924/00

Abstract: It is a general object of the present invention to provide an improved method of fabrication in the formation of an improved copper metal diffusion barrier layer having the structure, W/WSiN/WN, in single and dual damascene interconnect trench/contact via processing with 0.10 micron nodes for MOSFET and CMOS applications. The diffusion barrier is formed by depositing a tungsten nitride bottom layer, followed by an in situ SiH4/NH3 or SiH4/H2 soak forming a WSiN layer, and depositing a final top layer of tungsten. This invention is used to manufacture reliable metal interconnects and contact vias in the fabrication of MOSFET and CMOS devices for both logic and memory applications and the copper diffusion barrier formed, W/WSiN/WN, passes a stringent barrier thermal reliability test at 400° C. Pure single barrier layers, i.e., single layer WN, exhibit copper punch through or copper spiking during the stringent barrier thermal reliability test at 400° C.

Abstract translation: 本发明的一般目的是提供一种改进的制造方法，该方法是在单和双镶嵌互连沟槽/接触通孔加工中具有以下结构的W / WSiN / WN结构的改进的铜金属扩散阻挡层的形成 微米节点用于MOSFET和CMOS应用。 扩散阻挡层通过沉积氮化钨底层，随后形成SiH4 / NH3或SiH4 / H2浸泡形成WSiN层，并沉积钨的最终顶层形成。 本发明用于在逻辑和存储器应用的MOSFET和CMOS器件的制造中制造可靠的金属互连和接触孔，并且形成的铜扩散阻挡层W / WSiN / WN在400℃下通过严格的阻挡热可靠性测试 在400℃的严格的阻隔热可靠性试验期间，纯单层阻挡层，即单层WN，表现出铜冲穿或铜尖峰。

公开(公告)号：US10475759B2

公开(公告)日：2019-11-12

申请号：US13270776

申请日：2011-10-11

Applicant: Shin-Puu Jeng ,  Chen-Hua Yu ,  Jing-Cheng Lin

Inventor： Shin-Puu Jeng ,  Chen-Hua Yu ,  Jing-Cheng Lin

IPC: H01L23/488 ,  H01L25/11 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

Abstract: An embodiment is a structure comprising a substrate, a first die, and a second die. The substrate has a first surface. The first die is attached to the first surface of the substrate by first electrical connectors. The second die is attached to the first surface of the substrate by second electrical connectors. A size of one of the second electrical connectors is smaller than a size of one of the first electrical connectors.

公开(公告)号：US09679783B2

公开(公告)日：2017-06-13

申请号：US13208197

申请日：2011-08-11

Applicant: Jing-Cheng Lin ,  Chin-Chuan Chang ,  Jui-Pin Hung ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Jing-Cheng Lin ,  Chin-Chuan Chang ,  Jui-Pin Hung ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: B29C33/12 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/561 ,  B29C33/123 ,  H01L21/566 ,  H01L23/3121 ,  H01L24/96 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00

Abstract: A bottom chase and a top chase of a molding system form a cavity to house a molding carrier and one or more devices. The molding carrier is placed in a desired location defined by a guiding component. The guiding component may be entirely within the cavity, or extend above a surface of the bottom chase and extend over a contacting edge of the top chase and the bottom chase, so that there is a gap between the edge of the top chase and the edge of the molding carrier which are filled by molding materials to cover the edge of the molding carrier. Releasing components may be associated with the top chase and/or the bottom chase, which may be a plurality of tape roller with a releasing film, or a plurality of vacuum holes within the bottom chase, or a plurality of bottom pins with the bottom chase.

公开(公告)号：US09646942B2

公开(公告)日：2017-05-09

申请号：US13403511

申请日：2012-02-23

Applicant: Jing-Cheng Lin ,  Po-Hao Tsai

Inventor： Jing-Cheng Lin ,  Po-Hao Tsai

IPC: H01L23/00 ,  B23K1/00 ,  B23K101/42 ,  H01L23/498

CPC classification number: H01L24/11 ,  B23K1/0016 ,  B23K2101/42 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/3841 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2924/01047 ,  H01L2224/05552 ,  H01L2924/00

Abstract: The mechanisms for forming bumps on packaged dies and package substrates reduce variation of bump heights across the packaged dies and packaged substrates. Bumps are designed to have different widths to counter the higher plating current near edge(s) of dies or substrates. Bump sizes can be divided into different zones depending on the bump patterns and densities across the packaged die and/or substrates. Smaller bumps near edges reduce the thickness of plated film(s), which would have been thicker due to being near the edges. As a result, the bump heights across the packaged dies and/or substrates can be kept significantly constant and chip package can be properly formed.