公开(公告)号：US20050036269A1

公开(公告)日：2005-02-17

申请号：US10921383

申请日：2004-08-19

Applicant: Qing Ma ,  Peng Cheng ,  Valluri Rao

Inventor： Qing Ma ,  Peng Cheng ,  Valluri Rao

IPC: B81B7/00 ,  H03H3/007 ,  H03H9/10 ,  H03H9/24 ,  H01G4/00

CPC classification number: B81B7/0077 ,  H03H3/0072 ,  H03H9/1057 ,  H03H9/2405 ,  H03H9/2431 ,  H03H9/2457 ,  H03H9/2463 ,  H03H2009/02503 ,  H03H2009/02511

Abstract: A microelectromechanical (MEMS) resonator with a vacuum-cavity is fabricated using polysilicon-enabled release methods. A vacuum-cavity surrounding the MEMS beam is formed by removing release material that surrounds the beam and sealing the resulting cavity under vacuum by depositing a layer of nitride over the structure. The vacuum-cavity MEMS resonators have cantilever beams, bridge beams or breathing-bar beams.

Abstract translation: 具有真空腔的微机电（MEMS）谐振器是使用多晶硅启用释放方法制造的。 围绕MEMS光束的真空腔通过去除围绕光束的释放材料并通过在结构上沉积氮化层而在真空下密封所得空腔来形成。 真空腔MEMS谐振器具有悬臂梁，桥梁或呼吸杆梁。

公开(公告)号：US06621137B1

公开(公告)日：2003-09-16

申请号：US09687907

申请日：2000-10-12

Applicant: Qing Ma ,  Peng Cheng ,  Valluri Rao

Inventor： Qing Ma ,  Peng Cheng ,  Valluri Rao

IPC: H01L2900

CPC classification number: B81C1/00333 ,  H01G5/16 ,  H01G5/40 ,  H01L2224/48091 ,  Y10T428/24248 ,  H01L2924/00014

Abstract: The present invention relates to a chip package that includes a semiconductor device and at least one micro electromechanical structure (MEMS) such that the semiconductor device and the MEMS form an integrated package. One embodiment of the present invention includes a semiconductor device, a first MEMS device disposed in a conveyance such as a film, and a second MEMS device disposed upon the semiconductor device through a via in the conveyance. The present invention also relates to a process of forming a chip package that includes providing a conveyance such as a tape automated bonding (TAB) structure that may bold at least one MEMS device. The method is further carried out by disposing the conveyance over the active surface of the device in a manner that causes the at least one MEMS to communicate electrically to the active surface. Where appropriate, a sealing structure such as a solder ring may be used to protect the MEMS.

Abstract translation: 本发明涉及包括半导体器件和至少一个微机电结构（MEMS）的芯片封装，使得半导体器件和MEMS形成集成封装。 本发明的一个实施例包括半导体器件，设置在诸如膜的输送器中的第一MEMS器件，以及通过输送中的通孔设置在半导体器件上的第二MEMS器件。 本发明还涉及一种形成芯片封装的方法，其包括提供输送，例如可以使至少一个MEMS器件粗化的带自动键合（TAB）结构。 该方法进一步通过以使得至少一个MEMS与活性表面电连通的方式布置在器件的有效表面上的输送来进行。 在适当的情况下，可以使用诸如焊环的密封结构来保护MEMS。

公开(公告)号：US06600389B2

公开(公告)日：2003-07-29

申请号：US09870857

申请日：2001-05-30

Applicant: Qing Ma ,  Peng Cheng

Inventor： Qing Ma ,  Peng Cheng

IPC: H03H915

CPC classification number: H03H9/02393 ,  H03H3/0077 ,  H03H9/2463 ,  H03H2009/02496 ,  H03H2009/02511

Abstract: A method for forming a microelectromechanical (MEMS) resonator is disclosed. The method comprises first manufacturing a plurality of resonator structures. Each of the resonator structures differ from the others in a systematic manner, such as the length of the resonator structure. The resonance frequency of each of the resonator structures is determined. Then, a desired resonator structure is selected based upon the resonance frequency of the desired resonator structure.

公开(公告)号：US06596609B2

公开(公告)日：2003-07-22

申请号：US09740782

申请日：2000-12-19

Applicant: Peng Cheng ,  Brian S. Doyle

Inventor： Peng Cheng ,  Brian S. Doyle

IPC: H01L21265

CPC classification number: H01L21/28132 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32137 ,  H01L21/32139 ,  Y10S438/947

Abstract: A method of fabricating a feature on a substrate is disclosed. In a described embodiment the feature is the gate electrode of an MOS transistor. In this embodiment a polysilicon layer is formed on the substrate. Next, an edge definition layer of silicon nitride is formed on the feature layer. Then, a patterned edge definition layer of silicon dioxide is formed on the first edge definition layer. Then, a silicon nitride spacer is formed adjacent to an edge of the patterned second edge definition layer. Finally, the polysilicon layer is etched, forming the transistor gate electrode from the polysilicon that remains under the spacer.

Abstract translation: 公开了一种在衬底上制造特征的方法。 在所描述的实施例中，特征是MOS晶体管的栅电极。 在该实施例中，在衬底上形成多晶硅层。 接下来，在特征层上形成氮化硅的边缘限定层。 然后，在第一边缘限定层上形成图案化的二氧化硅边缘限定层。 然后，与图案化的第二边缘限定层的边缘相邻地形成氮化硅间隔物。 最后，蚀刻多晶硅层，从保留在间隔物下方的多晶硅形成晶体管栅电极。

公开(公告)号：US06570468B2

公开(公告)日：2003-05-27

申请号：US09895360

申请日：2001-06-29

Applicant: Qing Ma ,  Peng Cheng ,  Valluri R. Rao

Inventor： Qing Ma ,  Peng Cheng ,  Valluri R. Rao

IPC: H03H905

CPC classification number: H03H3/0077 ,  H03H9/2463 ,  Y10S977/70 ,  Y10S977/721 ,  Y10S977/733 ,  Y10S977/888 ,  Y10S977/889

Abstract: A method including to a resonator coupled to at least one support structure on a substrate, the resonator having a resonating frequency in response to a frequency stimulus, modifying the resonating frequency by modifying the at least one support structure. A method including forming a resonator coupled to at least one support structure on a chip-level substrate, the resonator having a resonating frequency; and modifying the resonating frequency of the resonator by modifying the at least one support structure. A method including applying a frequency stimulus to a resonator coupled to at least one support structure on a chip-level substrate determining a resonating frequency; and modifying the resonating frequency of the resonator by modifying the at least one support structure. An apparatus including a resonator coupled to at least one support structure on a chip-level substrate, the resonator having a resonating frequency tuned by the modification of the at least one support structure to a selected frequency stimulus.

Abstract translation: 一种方法，包括耦合到衬底上的至少一个支撑结构的谐振器，所述谐振器响应于频率刺激具有谐振频率，通过修改所述至少一个支撑结构来修改谐振频率。 一种方法，包括形成耦合到芯片级衬底上的至少一个支撑结构的谐振器，所述谐振器具有谐振频率; 以及通过修改所述至少一个支撑结构来修改谐振器的谐振频率。 一种方法，包括对耦合到芯片级衬底上的至少一个支撑结构的谐振器施加频率刺激，确定谐振频率; 以及通过修改所述至少一个支撑结构来修改谐振器的谐振频率。 一种包括耦合到芯片级衬底上的至少一个支撑结构的谐振器的谐振器，所述谐振器具有通过所述至少一个支撑结构的修改调谐到所选择的频率刺激的谐振频率。

公开(公告)号：US06528856B1

公开(公告)日：2003-03-04

申请号：US09212773

申请日：1998-12-15

Applicant: Gang Bai ,  David B. Fraser ,  Brian S. Doyle ,  Peng Cheng ,  Chunlin Liang

Inventor： Gang Bai ,  David B. Fraser ,  Brian S. Doyle ,  Peng Cheng ,  Chunlin Liang

IPC: H01L2976

CPC classification number: H01L29/513 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28211 ,  H01L21/28229 ,  H01L29/517

Abstract: A method of forming a dielectric layer suitable for use as the gate dielectric layer of a metal-oxide-semiconductor field effect transistor (MOSFET) includes oxidizing the surface of a silicon substrate, forming a metal layer over the oxidized surface, and reacting the metal with the oxidized surface to form a substantially intrinsic layer of silicon superjacent the substrate, wherein at least a portion of the silicon layer may be an epitaxial silicon layer, and a metal oxide layer superjacent the silicon layer. In a further aspect of the present invention, an integrated circuit includes a plurality of MOSFETs, wherein various ones of the plurality of transistors have metal oxide gate dielectric layers and substantially intrinsic silicon layers subjacent the metal oxide dielectric layers.

Abstract translation: 形成适合用作金属氧化物半导体场效应晶体管（MOSFET）的栅极电介质层的电介质层的方法包括氧化硅衬底的表面，在氧化表面上形成金属层，并使金属 与氧化表面形成超过衬底的基本上本征的硅层，其中硅层的至少一部分可以是外延硅层，以及位于硅层之上的金属氧化物层。 在本发明的另一方面，集成电路包括多个MOSFET，其中多个晶体管中的各个晶体管具有金属氧化物栅极电介质层和位于金属氧化物电介质层之下的基本上本征的硅层。

公开(公告)号：US06169298A

公开(公告)日：2001-01-02

申请号：US09131727

申请日：1998-08-10

Applicant: Ying-Fu Lin ,  Liang-Tung Chang ,  Shiang-Peng Cheng ,  Kuan-Chu Kuo ,  Chiao-Yun Lin ,  Fu-Chou Liu

Inventor： Ying-Fu Lin ,  Liang-Tung Chang ,  Shiang-Peng Cheng ,  Kuan-Chu Kuo ,  Chiao-Yun Lin ,  Fu-Chou Liu

IPC: H01L3300

CPC classification number: H01L33/02 ,  H01L33/14 ,  H01L33/30

Abstract: A semiconductor light emitting device, such as the light emitting diode (LED) or the laser diode (LD), having a structure in which a light emitting area is a double heterostructure or a multi-layer quantum well structure. The light emitting area is formed on a substrate. Subsequently, an electrically conductive oxide layer as a transparent window layer to eliminate the crowding effect is formed on the light emitting area. The substrate layer consists of a GaAs substrate and a GaAsP layer to increasing the band gap energy of the substrate. The electrically conductive oxide layer is formed of AlZnO(x) material, having a lower electrical resistivity and a high transparency in the visible wavelength region. The window layer is formed using a physical vapor deposition or a metalorganic chemical vapor deposition.

Abstract translation: 诸如发光二极管（LED）或激光二极管（LD）的半导体发光器件具有其中发光区域是双异质结构或多层量子阱结构的结构。 发光区域形成在基板上。 随后，在发光区域上形成作为透明窗口层的导电氧化物层以消除拥挤效应。 衬底层由GaAs衬底和GaAsP层组成，以增加衬底的带隙能量。 导电氧化物层由AlZnO（x）材料形成，具有较低的电阻率和可见光波长区域的高透明度。 窗层使用物理气相沉积或金属有机化学气相沉积形成。

公开(公告)号：US6121093A

公开(公告)日：2000-09-19

申请号：US164446

申请日：1998-09-30

Applicant: Peng Cheng ,  Brian Doyle

Inventor： Peng Cheng ,  Brian Doyle

IPC: H01L21/28 ,  H01L21/336

CPC classification number: H01L29/6659 ,  H01L21/28132 ,  H01L29/66651 ,  H01L29/66659 ,  Y10S438/945

Abstract: A method of forming an asymmetric transistor and an asymmetric transistor. The method includes patterning a first spacer material and a second spacer material over a gate electrode material on a substrate with one side of the second spacer material adjacent to a first spacer material. The gate electrode material is patterned according to the first spacer material and the second material. Junction regions are formed in the substrate adjacent to the gate electrode material. One of the first spacer material and the second spacer material is then removed and the gate electrode material is patterned into a gate electrode according to the other of the first spacer and the second spacer material. Finally, second junction regions are formed in the substrate adjacent to gate electrode.

Abstract translation: 一种形成不对称晶体管和不对称晶体管的方法。 该方法包括在衬底上的栅极电极材料上形成第一间隔物材料和第二间隔物材料，其中第二间隔物材料的一侧与第一间隔物材料相邻。 根据第一间隔物材料和第二材料对栅电极材料进行图案化。 在与栅电极材料相邻的衬底中形成结区。 然后去除第一间隔物材料和第二间隔物材料中的一个，并且根据第一间隔物和第二间隔物材料中的另一个将栅电极材料图案化成栅电极。 最后，在与栅电极相邻的衬底中形成第二结区。

公开(公告)号：US6017614A

公开(公告)日：2000-01-25

申请号：US157510

申请日：1998-09-21

Applicant: Kwong-Jr Tsai ,  Shiang-Peng Cheng ,  Yeur-Luen Tu ,  Ing-Ruey Liaw

Inventor： Kwong-Jr Tsai ,  Shiang-Peng Cheng ,  Yeur-Luen Tu ,  Ing-Ruey Liaw

IPC: H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L23/532 ,  B32B3/00

CPC classification number: H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/3145 ,  H01L21/31612 ,  H01L21/3185 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5329 ,  H01L21/76837 ,  H01L2924/0002 ,  Y10S438/938 ,  Y10T428/24917

Abstract: A method was achieved for forming a multilayer passivation layer comprised of a silicon oxide/silicon nitride/silicon oxide/silicon nitride by depositing the layers consecutively in a single PECVD system. The method consists of depositing a first SiO.sub.2 layer that serves as a stress-release layer, a thin Si.sub.3 N.sub.4 layer that serves as a buffer layer that minimizes cracking and as a passivation layer that prevents mobile alkaline ion penetration, a thin second SiO.sub.2 layer to fill and seal any remaining cracks and pinholes in the first Si.sub.3 N.sub.4 layer, and a main Si.sub.3 N.sub.4 passivation layer that prevents water and/or other corrosive chemicals from attacking the metal. Since this multilayer passivation layer can be deposited essentially pinhole-free to a thickness that is less than the prior art's passivation layer of 8000 Angstroms needed to prevent pinholes, it can be used on 0.38 to 0.25 um DRAM technology, which eliminates voids that could otherwise trap photoresist which can later cause corrosion of the metal lines.

Abstract translation: 通过在单个PECVD系统中连续沉积层来形成由氧化硅/氮化硅/氧化硅/氮化硅组成的多层钝化层的方法。 该方法包括沉积用作应力释放层的第一SiO 2层，用作最小化裂纹的缓冲层的薄Si 3 N 4层，以及防止移动碱性离子渗透的钝化层，稀的第二SiO 2层填充 并且密封第一Si 3 N 4层中的任何剩余的裂纹和针孔，以及防止水和/或其它腐蚀性化学物质侵蚀金属的主要Si 3 N 4钝化层。 由于这种多层钝化层可以基本上无针孔地沉积到比现有技术的防止针孔所需的8000埃的钝化层的厚度，所以它可以用于0.38到0.25微米的DRAM技术，这消除了否则的空隙 陷阱光致抗蚀剂可以后来导致金属线的腐蚀。

公开(公告)号：US06008507A

公开(公告)日：1999-12-28

申请号：US144908

申请日：1998-09-01

Applicant: Ying-Fu Lin ,  Liang-Tung Chang ,  Shiang-Peng Cheng ,  Kuan-Chu Kuo ,  Chiao-Yun Lin ,  Fu-Chou Liu

Inventor： Ying-Fu Lin ,  Liang-Tung Chang ,  Shiang-Peng Cheng ,  Kuan-Chu Kuo ,  Chiao-Yun Lin ,  Fu-Chou Liu

IPC: H01L33/10 ,  H01L33/30 ,  H01L33/00 ,  H01L31/0328

CPC classification number: H01L33/30 ,  H01L33/10

Abstract: A structure of a semiconductor light emitting device includes a GaAs substrate, a GaAsP interface substrate, a first cladding layer, an active layer, and a second cladding layer. The GaAsP interface substrate layer is formed on the GaAs substrate, in addition, the GaAsP interface substrate layer formed on the substrate is of a thickness such that the upper surface of the GaAsP interface substrate layer adjacent to the substrate is composed of single crystal. The first cladding layer of a first conductivity is formed on the GaAsP interface substrate layer. The active layer is formed on the first cladding layer, from which the light is generated in the active layer. The second cladding layer of a second conductivity is formed on the active layer.

Abstract translation: 半导体发光器件的结构包括GaAs衬底，GaAsP界面衬底，第一覆层，有源层和第二覆层。 在GaAs衬底上形成GaAsP界面衬底层，此外，形成在衬底上的GaAsP界面衬底层的厚度使得与衬底相邻的GaAsP界面衬底层的上表面由单晶构成。 在GaAsP界面基底层上形成第一导电性的第一覆层。 活性层形成在第一包覆层上，在活性层中产生光。 在有源层上形成第二导电性的第二覆层。