公开(公告)号：US08214658B2

公开(公告)日：2012-07-03

申请号：US12194620

申请日：2008-08-20

Applicant: Jon A. Casey ,  Michael S. Floyd ,  Soraya Ghiasi ,  Kenneth C. Marston ,  Jennifer V. Muncy ,  Malcolm S. Ware ,  Roger D. Weekly

Inventor： Jon A. Casey ,  Michael S. Floyd ,  Soraya Ghiasi ,  Kenneth C. Marston ,  Jennifer V. Muncy ,  Malcolm S. Ware ,  Roger D. Weekly

IPC: G06F1/00

CPC classification number: G06F1/3203 ,  G06F1/206 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/172

Abstract: Mitigating effects of delamination of components in the data processing system is provided. A signal is received from one or more sensors in the data processing system. A determination is made as to whether the signal indicates that one threshold in a plurality of thresholds has been reached or exceeded. Responsive to the signal indicating that one threshold in the plurality of thresholds has been reached or exceeded, a determination is made as to whether the one threshold is a low temperature threshold or a high temperature threshold. Responsive to the one threshold being a low temperature threshold, one of a plurality of actions is initiated to increase a temperature of the data processing system thereby mitigating effects of delamination of the components in the data processing system.

Abstract translation: 提供了数据处理系统中组件分层的缓解效应。 从数据处理系统中的一个或多个传感器接收信号。 确定信号是否指示已经达到或超过多个阈值中的一个阈值。 响应于指示已经达到或超过多个阈值中的一个阈值的信号，确定一个阈值是低温阈值还是高温阈值。 响应于一个阈值是低温阈值，开始多个动作之一以增加数据处理系统的温度，从而减轻数据处理系统中组件的分层影响。

公开(公告)号：US20120125677A1

公开(公告)日：2012-05-24

申请号：US12952152

申请日：2010-11-22

Applicant: Jinwoo Choi ,  Sungjun Chun ,  Jason L. Frankel ,  Paul R. Walling ,  Roger D. Weekly

Inventor： Jinwoo Choi ,  Sungjun Chun ,  Jason L. Frankel ,  Paul R. Walling ,  Roger D. Weekly

IPC: H05K1/11 ,  H05K3/10

CPC classification number: H05K1/0224 ,  G06F17/5081 ,  H05K1/116 ,  H05K2201/09681 ,  H05K2201/09718 ,  H05K2201/09727 ,  Y10T29/49004 ,  Y10T29/49155 ,  Y10T29/53022

Abstract: A first selection of mesh line segments of a mesh layer are of a first width and a second selection of mesh line segments of the mesh layer are of a second width, wherein the second width is greater than the first width. The second selection of mesh line segments of the second width are positioned in parallel to a selection of signal lines in a signal layer that are likely to introduce crosstalk, wherein the widening of the mesh line segments shadowing the selection of signal lines increases the likelihood that the return current associated with the signal will flow in the wider mesh line segment, thereby increasing the likelihood of containing the electromagnetic fields associated with the signal such that crosstalk to other signals is reduced or contained.

Abstract translation: 网格层的网格线段的第一选择是第一宽度，并且网格层的网格线段的第二选择具有第二宽度，其中第二宽度大于第一宽度。 第二宽度的网格线段的第二选择与信号层中可能引入串扰的信号线的选择平行地布置，其中遮蔽信号线选择的网线段的加宽增加了 与信号相关联的返回电流将在更宽的网格线段中流动，从而增加了包含与信号相关联的电磁场的可能性，使得与其他信号的串扰减少或包含。

公开(公告)号：US20120081873A1

公开(公告)日：2012-04-05

申请号：US12895251

申请日：2010-09-30

Applicant: Douglas A. Baska ,  Daniel M. Dreps ,  Rohan U. Mandrekar ,  Roger D. Weekly

Inventor： Douglas A. Baska ,  Daniel M. Dreps ,  Rohan U. Mandrekar ,  Roger D. Weekly

IPC: H05K1/11 ,  H05K3/10

CPC classification number: H05K3/4623 ,  H05K1/0216 ,  H05K1/141 ,  H05K3/368 ,  H05K2201/10189 ,  Y10T29/49126 ,  Y10T29/49162 ,  Y10T29/53004

Abstract: Some embodiments of the inventive subject matter are directed to a first circuit board configured to include an electronic component. The electronic component includes a plurality of leads. The first circuit board includes first wires configured to connect to a first portion of the plurality of leads. The second circuit board is affixed to the first circuit board. The second circuit board includes second wires. The second circuit board is smaller in size than the first circuit board. A plurality of electrical connectors extend through a thickness of the first circuit board and are configured to connect a second portion of the plurality of leads to the second wires.

Abstract translation: 本发明的一些实施例涉及被配置为包括电子部件的第一电路板。 电子部件包括多个引线。 第一电路板包括被配置为连接到多个引线的第一部分的第一布线。 第二电路板固定在第一电路板上。 第二电路板包括第二导线。 第二个电路板的尺寸比第一个电路板小。 多个电连接器延伸穿过第一电路板的厚度，并且被配置为将多个引线的第二部分连接到第二导线。

公开(公告)号：US07849427B2

公开(公告)日：2010-12-07

申请号：US12021363

申请日：2008-01-29

Applicant: Michael A. Christo ,  Julio A. Maldonado ,  Roger D. Weekly ,  Tingdong Zhang

Inventor： Michael A. Christo ,  Julio A. Maldonado ,  Roger D. Weekly ,  Tingdong Zhang

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  H05K1/0237 ,  H05K3/0005 ,  H05K2201/09236 ,  H05K2201/09672

Abstract: An auto routing method and system provides optimized circuit routing while maintaining proper reference return paths for critical signals. Critical signal paths are auto-routed simultaneously with corresponding reference return paths, and the reference return paths can be merged into reference planes if they are adjacent to regions connected to the same reference net. The reference return paths may be in a plane adjacent to the signal path plane in the same channel, or the reference returns may be routed in adjacent channels in the same plane as the signal path. A check may be performed on endpoints of each critical signal path to determine whether a reference return via is present within a proximity tolerance of the signal path endpoints, and a reference return via placed if not.

Abstract translation: 自动路由方法和系统提供优化的电路路由，同时为关键信号保留适当的参考返回路径。 临界信号路径与对应的参考返回路径同时自动路由，并且如果参考返回路径与连接到相同参考网络的区域相邻，则它们可以合并到参考平面中。 参考返回路径可以在与相同信道中的信号路径平面相邻的平面中，或者参考返回可以在与信号路径相同的平面中的相邻信道中路由。 可以在每个关键信号路径的端点上执行检查，以确定参考返回通道是否存在于信号路径端点的接近容限内，如果不是则通过放置参考返回。

公开(公告)号：US20100261346A1

公开(公告)日：2010-10-14

申请号：US12823316

申请日：2010-06-25

Applicant: Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

Inventor： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

IPC: H01L21/768 ,  G06F17/50

CPC classification number: G06F17/5077 ,  H05K1/0219 ,  H05K1/0237 ,  H05K1/0253 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/09536 ,  H05K2201/09672 ,  H05K2201/0969 ,  H05K2201/09718 ,  Y10T29/49117 ,  Y10T29/49153 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24322

Abstract: Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.

Abstract translation: 具有带状段互连的通孔上的参考平面空隙的制造电路允许在通孔上路由关键信号路径，同时仅通过插入电容略微增加。 传输线参考平面定义了通过刚性衬底芯的信号承载电镀通孔（PTH）上方（或下方）的空隙，使得信号不会被阻抗失配降级，否则会由分流电容引起 信号承载PTH的顶部（或底部）到传输线参考平面。 为了提供增加的布线密度，信号路径被布置在空隙上，但是通过将导电条包括在通过空隙减少与信号承载PTH的耦合并且维持 信号路径导体。

公开(公告)号：US07720621B2

公开(公告)日：2010-05-18

申请号：US11847557

申请日：2007-08-30

Applicant: Roger D. Weekly

Inventor： Roger D. Weekly

IPC: G01R19/00

CPC classification number: G06F1/3203 ,  G06F1/329 ,  Y02D10/24

Abstract: A method and system for applying multiple voltage droop detection and instruction throttling instances with customized thresholds across semiconductor chips. Environmental parameters are detected for various locations on a chip, and timing margins are determined for each location on the chip. An acceptable voltage droop for each location is determined based on the environmental parameters and the timing margins for the corresponding location. A droop threshold is then determined for each location based on the corresponding acceptable voltage droop determined for the corresponding location.

Abstract translation: 一种用于跨半导体芯片应用具有定制阈值的多个电压下降检测和指令调节实例的方法和系统。 检测芯片上各个位置的环境参数，并为芯片上的每个位置确定定时裕度。 基于相应位置的环境参数和定时裕度来确定每个位置的可接受电压下降。 然后基于为相应位置确定的相应的可接受电压下降，为每个位置确定下垂阈值。

公开(公告)号：US20100049995A1

公开(公告)日：2010-02-25

申请号：US12194620

申请日：2008-08-20

Applicant: Jon A. Casey ,  Michael S. Floyd ,  Soraya Ghiasi ,  Kenneth C. Marston ,  Jennifer V. Muncy ,  Malcolm S. Ware ,  Roger D. Weekly

Inventor： Jon A. Casey ,  Michael S. Floyd ,  Soraya Ghiasi ,  Kenneth C. Marston ,  Jennifer V. Muncy ,  Malcolm S. Ware ,  Roger D. Weekly

IPC: G06F1/00

CPC classification number: G06F1/3203 ,  G06F1/206 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/172

Abstract: Mitigating effects of delamination of components in the data processing system is provided. A signal is received from one or more sensors in the data processing system. A determination is made as to whether the signal indicates that one threshold in a plurality of thresholds has been reached or exceeded. Responsive to the signal indicating that one threshold in the plurality of thresholds has been reached or exceeded, a determination is made as to whether the one threshold is a low temperature threshold or a high temperature threshold. Responsive to the one threshold being a low temperature threshold, one of a plurality of actions is initiated to increase a temperature of the data processing system thereby mitigating effects of delamination of the components in the data processing system.

Abstract translation: 提供了数据处理系统中组件分层的缓解效应。 从数据处理系统中的一个或多个传感器接收信号。 确定信号是否指示已经达到或超过多个阈值中的一个阈值。 响应于指示已经达到或超过多个阈值中的一个阈值的信号，确定一个阈值是低温阈值还是高温阈值。 响应于一个阈值是低温阈值，开始多个动作之一以增加数据处理系统的温度，从而减轻数据处理系统中组件的分层影响。

公开(公告)号：US20100049466A1

公开(公告)日：2010-02-25

申请号：US12194606

申请日：2008-08-20

Applicant: Jon A. Casey ,  Michael S. Floyd ,  Soraya Ghiasi ,  Kenneth C. Marston ,  Jennifer V. Muncy ,  Malcom S. Ware ,  Roger D. Weekly

Inventor： Jon A. Casey ,  Michael S. Floyd ,  Soraya Ghiasi ,  Kenneth C. Marston ,  Jennifer V. Muncy ,  Malcom S. Ware ,  Roger D. Weekly

IPC: G06F17/00 ,  G08B1/08

CPC classification number: G06F11/3058

Abstract: Monitoring temperature excursions an assembly experiences over a life of the assembly is provided. A determination is made as to whether the assembly has been in service beyond a predetermined end of life objective. Responsive to the assembly failing to be in service beyond the predetermined end of life objective, a new temperature value associated with the assembly is read. A modifier value for a figure of merit (FOM) value is computed and added to a cumulative figure of merit value. The cumulative figure of merit value is compared to a cumulative stress figure of merit budget. Responsive to the cumulative figure of merit value exceeding the cumulative stress figure of merit budget, an identified stress management solution is implemented.

Abstract translation: 提供了组装过程中组装体验的温度偏移。 确定组件是否已经超出预定寿命目标的使用。 响应于组装不能超过预定寿命目标的服务，读取与组件相关联的新的温度值。 计算品质因数（FOM）值的修饰符值，并将其添加到累积品质因数值。 将累积的绩效值与累积压力的绩效预算进行比较。 响应累积绩效值超过累积压力的绩效预算数量，实施了一个确定的压力管理解决方案。

公开(公告)号：US07614141B2

公开(公告)日：2009-11-10

申请号：US11355713

申请日：2006-02-16

Applicant: Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm B. O'Reilly ,  Roger D. Weekly

Inventor： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm B. O'Reilly ,  Roger D. Weekly

IPC: H01K3/10

CPC classification number: H05K1/162 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/09609 ,  H05K2201/09627 ,  Y10T29/49117 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A low inductance via arrangement for multilayer ceramic (MLC) substrates is provided. With the MLC substrate and via arrangement of the illustrative embodiments, the via-field inductance for a given contact pad array is reduced. This reduction is achieved by the introduction of T-jogs and additional vias. These T-jogs and additional vias form additional current paths that cause additional parallel inductances that reduce the via-field inductance. In one illustrative embodiment, the additional T-jogs and vias are added to a center portion of a contact pad array. The T-jogs are comprised of two jogs in a wiring layer of the MLC, each jog being toward a via associated with an adjacent contact pad in the contact pad array. These additional T-jogs and vias form additional current loops parallel to the existing ones which thus, reduce the total inductance of the via-field.

Abstract translation: 提供了一种用于多层陶瓷（MLC）衬底的低电感通孔布置。 通过MLC衬底和示例性实施例的通孔布置，给定接触焊盘阵列的通孔电感减小。 这种减少是通过引入T-jogs和附加通孔来实现的。 这些T形点动和附加通孔形成额外的电流路径，从而产生额外的并联电感，从而减小通路电感。 在一个说明性实施例中，附加的T形点动和通孔被添加到接触焊盘阵列的中心部分。 T-jogs由MLC的布线层中的两个点动组成，每个点动都朝向与接触垫阵列中的相邻接触焊盘相关联的通孔。 这些额外的T形点动和通孔形成与现有循环平行的额外的电流回路，从而减小通孔的总电感。

公开(公告)号：US20090031270A1

公开(公告)日：2009-01-29

申请号：US11829179

申请日：2007-07-27

Applicant: Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Roger D. Weekly

Inventor： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Roger D. Weekly

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  H05K1/0216 ,  H05K1/115 ,  H05K3/0005 ,  H05K2201/09636

Abstract: A design method and system for minimizing blind via current loops provides for improvement of electrical interconnect structure design without requiring extensive electromagnetic analysis. Other vias in the vicinity of a blind via carrying a critical signal are checked for suitability to conduct return current corresponding to the critical signal that is disrupted by the transition from a layer between two metal planes to another layer. The distance to the return current via(s) is checked and the design is adjusted to reduce the distance if the distance is greater than a specified threshold. If the blind via transition is to an external layer, suitable vias connect the reference plane at the internal end of the blind via to an external terminal. If the transition is between internal layers, suitable vias are vias that connect the two reference planes surrounding the reference plane traversed by the blind via.

Abstract translation: 用于最小化盲通过电流回路的设计方法和系统提供了电互连结构设计的改进，而不需要广泛的电磁分析。 检查通过携带关键信号的盲目附近的其他通孔是否​​适合于进行对应于由两个金属平面之间的层到另一层之间的过渡而被破坏的关键信号的返回电流。 检查通过（s）的返回电流的距离，并且如果距离大于指定的阈值，则设计被调整以减小距离。 如果盲目通过转换到外部层，合适的通孔将盲通孔内部的参考平面连接到外部端子。 如果过渡在内层之间，合适的通孔是连接围绕由盲孔通过的参考平面的两个参考平面的通孔。