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公开(公告)号：US20180269316A1
公开(公告)日：2018-09-20
申请号：US15760579
申请日：2016-08-29
IPC分类号： H01L29/778 , H01L29/20 , H01L21/02 , H01L29/66 , H01L29/36
CPC分类号： H01L29/7787 , H01L21/0254 , H01L29/2003 , H01L29/36 , H01L29/66431 , H01L29/66462 , H01L29/7786
摘要： A semiconductor base substance includes: a substrate; a buffer layer which is made of a nitride semiconductor and provided on the substrate; and a channel layer which is made of a nitride semiconductor and provided on the buffer layer, wherein the buffer layer includes: a first region which is provided on the substrate side and has boron concentration higher than acceptor element concentration; and a second region which is provided on the first region, and has boron concentration lower than that in the first region and acceptor element concentration higher than that in the first region. As a result, the semiconductor base substance which can obtain a high pit suppression effect while maintaining a high longitudinal breakdown voltage is provided.
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42.发明申请公开(公告)号：US20180266011A1
公开(公告)日：2018-09-20
申请号：US15761495
申请日：2016-09-20
发明人： Taiki YAMADA , Naoki MASUDA
摘要： A single-crystal manufacturing apparatus including: at least two different melt surface position measuring means for measuring a melt surface position of a material melt; controlling means for controlling the melt surface position based on the measured melt surface position; and determining means for determining whether a measurement abnormality has occurred in the melt surface position measuring means, the apparatus being characterized in that the melt surface position is measured by the plurality of melt surface position measuring means at the same time, one melt surface position measuring means adopted for control over the melt surface position is selected from the plurality of melt surface position measuring means, and the melt surface position measuring means adopted for control over the melt surface position is switched to another melt surface position measuring means when the determining means determines that a measurement abnormality has occurred in the selected melt surface measuring means.
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公开(公告)号：US20180247851A1
公开(公告)日：2018-08-30
申请号：US15754410
申请日：2016-08-18
发明人： Shiroyasu WATANABE
IPC分类号： H01L21/68 , G01N23/207 , G01N23/20008
CPC分类号： H01L21/68 , G01N23/20008 , G01N23/207 , G01N2223/6116
摘要： A method for determining front and back of a single-crystal wafer including: using, as the single-crystal wafer, one having a crystal plane which is laterally asymmetrical to a reference direction connecting a center of a cut for orientation identification formed in an end face of the single-crystal wafer with a center of the single-crystal wafer; noticing the laterally asymmetrical crystal plane, applying an X-ray to the single-crystal wafer, and detecting a diffracted X-ray to measure an angle formed between an orientation of the noticed crystal plane and the reference direction; and determining whether a surface of the single-crystal wafer is a front surface or a back surface from a value of the measured angle. Consequently, the method for determining a front and a back of a single-crystal wafer which can assuredly determine the front and the back of the single-crystal wafer and is superior in cost can be provided.
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公开(公告)号：US10054554B2
公开(公告)日：2018-08-21
申请号：US15573058
申请日：2016-03-09
发明人： Masahiro Kato
CPC分类号： G01N21/9501 , G01B11/30 , G01N21/8851 , G01N21/94 , G01N21/956 , G01N2021/8822 , G01N2021/8864 , G01N2021/8867 , G01N2021/8874 , G01N2021/8877 , G01N2201/06113 , H01L22/00
摘要： A method for evaluating a semiconductor wafer includes detecting semiconductor wafer LPDs as an examination sample in two measurement modes, performing size classification of the LPDs, calculating a distance between detection coordinates and a relative angle in the two measurement modes, presetting determination criteria to determine each LPD as a foreign matter or killer defect in accordance with each classified size, detecting semiconductor wafer LPDs as an evaluation target in the two measurement modes, performing size classification of the LPDs as the evaluation target, calculating a distance between detection coordinates and a relative angle of the evaluation target, and classifying the LPDs detected on a surface of the evaluation target into the killer defect and the foreign mater based on a result of the calculation and the determination criteria. The method enables classifying all LPDs from which quantitative size information cannot be provided, into the killer defect and foreign matter.
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公开(公告)号：US10036100B2
公开(公告)日：2018-07-31
申请号：US15112653
申请日：2015-02-03
CPC分类号： C30B15/203 , C30B15/14 , C30B15/20 , C30B15/22 , C30B29/06
摘要： An apparatus for producing a silicon single crystal by a Czochralski method with a chamber having a heater therein to heat a raw material and to cool the chamber by a coolant, including: measuring an inlet temperature, outlet temperature, and flow rate in a passage of the coolant to cool the chamber with flowing in the chamber; calculating a removed heat quantity from the chamber based on the measured values of the inlet temperature, outlet temperature, and flow rate; controlling heater power based on the value of the removed heat quantity. This provides an apparatus which can pull a single crystal in a crystal diameter and a crystal pulling rate closer to the target values by controlling the heater power based on a removed heat quantity from the chamber calculated by the measured values of temperatures and a flow rate of the coolant.
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公开(公告)号：US10029392B2
公开(公告)日：2018-07-24
申请号：US15027157
申请日：2014-10-27
发明人： Keiichi Kanbayashi
摘要： A method for slicing workpiece reusing a wire used for previous slicing of a workpiece to slice a subsequent workpiece by which the workpiece is pressed against a wire row and sliced, the wire row being formed of the wire spirally wound between a plurality of wire guides and travels in an axial-direction, where wire tension at the time of slicing the workpiece is set to a value in the range of 87 to 95% of wire tension in the previous slicing of the workpiece, a new wire supply amount at the time of slicing the workpiece is set to a value in the range of 125% or more of a new wire supply amount in the previous slicing of the workpiece, and the wire is reused to slice the subsequent workpiece.
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公开(公告)号：US20180144975A1
公开(公告)日：2018-05-24
申请号：US15574326
申请日：2016-03-08
发明人： Isao YOKOKAWA , Hiroji AGA , Norihiro KOBAYASHI
IPC分类号： H01L21/762 , H01L21/20 , H01L27/12
CPC分类号： H01L21/76254 , H01L21/02 , H01L21/2007 , H01L27/12 , H01L27/1203
摘要： A method for producing a SOI wafer that includes implanting at least one type of gas ion selected from a hydrogen ion and a rare gas ion from a surface of a bond wafer formed of a silicon single crystal to form an ion implanted layer, bonding the ion-implanted surface of the bond wafer to a surface of a base wafer formed of a silicon single crystal through a silicon oxide film formed on the base wafer surface, delaminating the bond wafer at the ion implanted layer by performing delamination heat treatment to fabricate a SOI wafer having a buried oxide film layer and a SOI layer on the base wafer, and performing flattening heat treatment on the SOI wafer in an atmosphere containing argon gas.
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48.发明授权公开(公告)号：US09966259B2
公开(公告)日：2018-05-08
申请号：US15585518
申请日：2017-05-03
发明人： Hiroshi Shikauchi , Ken Sato , Hirokazu Goto , Masaru Shinomiya , Keitaro Tsuchiya , Kazunori Hagimoto
IPC分类号： H01L21/02 , H01L29/36 , H01L21/225 , C30B25/18 , C30B29/06 , C30B29/40 , H01L29/778 , H01L29/66
CPC分类号： H01L21/02658 , C30B23/025 , C30B25/18 , C30B25/186 , C30B29/06 , C30B29/403 , H01L21/02381 , H01L21/0245 , H01L21/0254 , H01L21/0259 , H01L21/02595 , H01L21/02598 , H01L21/2251 , H01L21/2258 , H01L29/36 , H01L29/66462 , H01L29/7786
摘要： A silicon-based substrate on which a nitride compound semiconductor layer is formed on a front surface thereof, including a first portion provided on the front surface side which has a first impurity concentration and a second portion provided on an inner side of the first portion which has a second impurity concentration higher than the first impurity concentration, wherein the first impurity concentration being 1×1014 atoms/cm3 or more and less than 1×1019 atoms/cm3. Consequently, there is provided the silicon-based substrate in which the crystallinity of the nitride compound semiconductor layer formed on an upper side thereof can be maintained excellently while improving a warpage of the substrate.
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公开(公告)号：US09938638B2
公开(公告)日：2018-04-10
申请号：US15121177
申请日：2015-02-10
发明人： Kazunori Hagimoto , Masaru Shinomiya , Keitaro Tsuchiya , Hirokazu Goto , Ken Sato , Hiroshi Shikauchi , Shoichi Kobayashi , Hirotaka Kurimoto
IPC分类号： C30B33/00 , H01L21/02 , H01L21/78 , H01L29/20 , C23C16/34 , C23C16/56 , C30B25/18 , C30B29/40 , C30B33/10 , H01L29/32 , H01L21/66 , C30B25/00
CPC分类号： C30B33/00 , C23C16/34 , C23C16/56 , C30B25/00 , C30B25/183 , C30B29/406 , C30B33/10 , H01L21/02013 , H01L21/02019 , H01L21/02021 , H01L21/02024 , H01L21/02378 , H01L21/02381 , H01L21/02458 , H01L21/0254 , H01L21/0262 , H01L21/7806 , H01L22/12 , H01L22/20 , H01L29/2003 , H01L29/32
摘要： A method for producing a semiconductor epitaxial wafer, including steps of: fabricating an epitaxial wafer by epitaxially growing a semiconductor layer on a silicon-based substrate; observing the outer edge portion of the fabricated epitaxial wafer; and removing portions in which a crack, epitaxial layer peeling, and a reaction mark observed in the step of observing are present. As a result, a method for producing a semiconductor epitaxial wafer in which a completely crack-free semiconductor epitaxial wafer can be obtained, is provided.
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公开(公告)号：US09935021B2
公开(公告)日：2018-04-03
申请号：US14890687
申请日：2014-04-14
发明人： Tsuyoshi Ohtsuki
CPC分类号： H01L22/14 , H01L22/12 , H01L29/0688
摘要： A method for evaluating a semiconductor wafer including preparing a reference wafer in which contamination element and amount of contamination are known, forming a plurality of cells including p-n junctions on the reference wafer, measuring junction leakage currents in the plurality of cells on the reference wafer to acquire a distribution of the junction leakage currents of the reference wafer, associating the distribution of the junction leakage currents of the reference wafer with a contamination element, forming a plurality of cells including p-n junctions on a wafer to be measured, measuring junction leakage currents in the plurality of cells on the wafer to be measured to acquire a distribution of the junction leakage currents of the wafer to be measured, and identifying a contamination element of the wafer to be measured based on the association.
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