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53 条记录 (耗时 0.018 秒)

    Semiconductor memory device
    42.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5715192A

    公开(公告)日：1998-02-03

    申请号：US502947

    申请日：1995-07-17

    申请人： Takehiro Hasegawa ,  Fujio Masuoka

    发明人： Takehiro Hasegawa ,  Fujio Masuoka

    IPC分类号： G11C11/41 ,  G11C11/40 ,  G11C11/412 ,  G11C11/34

    CPC分类号： G11C11/40 ,  G11C11/412

    摘要： A plurality of static memory cells including CMOS flip-flops and switching MOS transistors are connected in series, thereby forming a memory cell unit in which one end of data reading is connected to bit lines. A series of the memory cell units are arranged, thereby forming a memory cell array. Reset terminals are provided for releasing cell data and causing the cell to function temporarily as a transfer gate of data.

    摘要翻译： 包括CMOS触发器和开关MOS晶体管的多个静态存储单元串联连接，从而形成其中数据读取的一端连接到位线的存储单元单元。 布置一系列存储单元单元，从而形成存储单元阵列。 提供复位端子用于释放单元数据并使单元临时工作作为数据传输门。

    Semiconductor memory device using dynamic type memory cells
    43.
    发明授权
    Semiconductor memory device using dynamic type memory cells 失效
    半导体存储器件采用动态型存储单元

    公开(公告)号：US5661678A

    公开(公告)日：1997-08-26

    申请号：US570966

    申请日：1995-12-12

    申请人： Masako Yoshida ,  Yukihito Oowaki ,  Takehiro Hasegawa ,  Kiyofumi Ochii ,  Masayuki Koizumi

    发明人： Masako Yoshida ,  Yukihito Oowaki ,  Takehiro Hasegawa ,  Kiyofumi Ochii ,  Masayuki Koizumi

    IPC分类号： H01L21/8242 ,  G11C11/404 ,  G11C11/405 ,  H01L27/108 ,  G11C7/00

    CPC分类号： G11C11/404 ,  H01L27/108 ,  H01L27/10808 ,  H01L27/10829

    摘要： A semiconductor memory device comprises a memory cell array including NAND type memory cell units arranged in matrix and having a plurality of dynamic type memory cells connected in series, a plurality of word lines, a plurality of bit lines arranged within the memory cell array, the plurality of bit lines including a bit line pairs which are arranged adjacent to each other or between which at least one bit line is interposed, and a plurality of sense amplifiers of a folded bit line type, provided in each of the plurality of bit line pairs, in which the memory cells are provided in positions corresponding to intersections of the bit lines and the word lines, and complementary data are written to two memory cells connected to each of the plurality of bit line pairs and one word line, and the two memory cells store one-bit data.

    摘要翻译： 半导体存储器件包括存储单元阵列，其包括以矩阵形式布置的NAND型存储单元单元，并且具有串联连接的多个动态型存储单元，多个字线，布置在存储单元阵列内的多个位线， 多个位线包括彼此相邻布置或位于其中的至少一个位线之间布置的位线对以及设置在多个位线对中的每一个中的折叠位线类型的多个读出放大器 其中存储单元被提供在与位线和字线的交点对应的位置中，并且互补数据被写入连接到多个位线对和一个字线中的每一个的两个存储器单元，并且两个存储器 单元存储一位数据。

    Semiconductor memory device having register groups for writing and reading data
    45.
    发明授权
    Semiconductor memory device having register groups for writing and reading data 失效
    具有用于写入和读取数据的寄存器组的半导体存储器件

    公开(公告)号：US5467303A

    公开(公告)日：1995-11-14

    申请号：US380443

    申请日：1995-01-30

    申请人： Takehiro Hasegawa ,  Shigeyoshi Watanabe ,  Fujio Masuoka

    发明人： Takehiro Hasegawa ,  Shigeyoshi Watanabe ,  Fujio Masuoka

    IPC分类号： G11C11/405 ,  G11C11/401 ,  G11C11/404 ,  G11C11/4096 ,  G11C11/24 ,  G11C7/00

    CPC分类号： G11C11/4096 ,  G11C11/404

    摘要： A semiconductor memory device comprises an array of memory cell units, each of which has a plurality of MOS transistors connected in series and a plurality of information storage capacitors corresponding in number to the MOS transistors and each having its one end connected to the source of a corresponding one of the MOS transistors, and a plurality of register groups each of which is adapted to temporarily store information stored in one of the memory cell units for each column of the array in order to read from and write into each memory cell unit.

    摘要翻译： 半导体存储器件包括一组存储单元单元，每个存储单元单元具有串联连接的多个MOS晶体管和多个与MOS晶体管相对应的多个信息存储电容器，每个信号存储电容器的一端连接到 对应的一个MOS晶体管，以及多个寄存器组，每个寄存器组适于临时存储存储在阵列的每列的存储单元单元之一中的信息，以便从每个存储单元单元读取和写入。

    Semiconductor integrated circuit
    46.
    发明授权
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号：US5373200A

    公开(公告)日：1994-12-13

    申请号：US214678

    申请日：1994-03-21

    申请人： Takehiro Hasegawa ,  Atsushi Kameyama

    发明人： Takehiro Hasegawa ,  Atsushi Kameyama

    IPC分类号： H03K3/02 ,  H03K3/012 ,  H03K3/037 ,  H03K5/13 ,  H03K19/20

    CPC分类号： H03K3/012 ,  H03K3/037 ,  H03K3/0372

    摘要： A semiconductor integrated circuit according to this invention is characterized by comprising a flip-flop having input terminal means and output terminal means, at least one input gate means having output terminal means connected to the input terminal means, which supplies data to this input terminal means under the control of clock, and at least one output buffer means having input terminal means connected to the output terminal means, to which the output signal of the flip-flop is supplied and which is connected to the output terminal means of the input gate means to receive the data from this input gate means to provide an advance read function.

    摘要翻译： 根据本发明的半导体集成电路的特征在于包括具有输入端子装置和输出端子装置的触发器，至少一个输入栅极装置，其具有连接到输入端子装置的输出端子装置，该输入端子装置向该输入端子装置 在时钟的控制下，以及至少一个输出缓冲装置，其具有连接到输出端装置的输入端装置，触发器的输出信号被提供给输入端装置，并连接到输入端口装置的输出端装置 从该输入门装置接收数据以提供预读功能。

    Semiconductor integrated circuit device with a stacked gate including a floating gate and a control gate
    48.
    发明授权
    Semiconductor integrated circuit device with a stacked gate including a floating gate and a control gate 失效
    具有包括浮动栅极和控制栅极的堆叠栅极的半导体集成电路器件

    公开(公告)号：US07672164B2

    公开(公告)日：2010-03-02

    申请号：US12027744

    申请日：2008-02-07

    申请人： Takehiro Hasegawa ,  Akira Umezawa ,  Koji Sakui ,  Fumitaka Arai ,  Ryo Mitani

    发明人： Takehiro Hasegawa ,  Akira Umezawa ,  Koji Sakui ,  Fumitaka Arai ,  Ryo Mitani

    IPC分类号： G11C16/04

    CPC分类号： H01L27/11524 ,  G11C11/005 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/20 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546

    摘要： A semiconductor integrated circuit device includes first and second nonvolatile semiconductor memories. The first memory has first and second select transistors and first memory cell transistors. The first memory cell transistor has a first floating gate on a first gate insulating film and a first control gate on a first inter-gate insulating film. The second memory has a third select transistor and a second memory cell transistor. The second memory cell transistor has a second floating gate on a second gate insulating film and a second control gate on a second inter-gate insulating film. The first and second gate insulating films have the same film thickness. The first and second floating gates have the same film thickness. The first and second inter-gate insulating films have the same film thickness. The first and second control gates have the same film thickness.

    摘要翻译： 半导体集成电路器件包括第一和第二非易失性半导体存储器。 第一存储器具有第一和第二选择晶体管和第一存储单元晶体管。 第一存储单元晶体管在第一栅极绝缘膜上具有第一浮置栅极，在第一栅极间绝缘膜上具有第一控制栅极。 第二存储器具有第三选择晶体管和第二存储单元晶体管。 第二存储单元晶体管在第二栅极绝缘膜上具有第二浮置栅极，在第二栅极绝缘膜上具有第二控制栅极。 第一和第二栅极绝缘膜具有相同的膜厚度。 第一和第二浮栅具有相同的膜厚度。 第一和第二栅极间绝缘膜具有相同的膜厚度。 第一和第二控制栅具有相同的膜厚度。

    Electric Compressor
    49.
    发明申请
    Electric Compressor 有权
    电动压缩机

    公开(公告)号：US20090129954A1

    公开(公告)日：2009-05-21

    申请号：US11915931

    申请日：2006-05-02

    申请人： Takehiro Hasegawa

    发明人： Takehiro Hasegawa

    IPC分类号： F04B35/04

    CPC分类号： F04C29/0085 ,  F04C2240/45 ,  F04C2240/803 ,  H01R13/6271 ,  H01R13/639 ,  H02K5/12 ,  H02K5/225

    摘要： An electric compressor incorporating an electric motor for driving a compression mechanism and containing, in a compressor housing, a joint between an external terminal for supplying power to the electric motor and an end of a wire from a stator of the electric motor. The electric compressor has a vibration proof means mechanically preventing at least one of disconnection, electrical instantaneous interruption, and damage on an insulating member that are caused by vibration at the joint and/or the vicinity of the joint. The vibration proof means can adopt various structures. When such a mechanical vibration proof means is provided in the electric compressor, vibration proof performance can be enhanced at the joint of a motor terminal with good productivity achieved, and occurrence of disconnection and instantaneous interruption of the terminal joint can be prevented.

    摘要翻译： 一种电动压缩机，其包括用于驱动压缩机构的电动机，并且在压缩机壳体中容纳用于向电动机供电的外部端子与来自电动机的定子的电线的端部之间的接头。 电动压缩机具有机械地防止由接头和/或接头附近的振动引起的绝缘构件的断开，电瞬间中断和损坏中的至少一种的防振装置。 防振装置可以采用各种结构。 当在电动压缩机中设置这样的机械防振装置时，可以在实现良好生产率的电动机端子的接头处提高防振性能，并且可以防止端子接头的断开和瞬时中断的发生。