公开(公告)号：US10343907B2

公开(公告)日：2019-07-09

申请号：US14660789

申请日：2015-03-17

Applicant: ASM IP Holding B.V.

Inventor： Bert Jongbloed ,  Dieter Pierreux ,  Cornelius A. van der Jeugd ,  Lucian Jdira ,  Radko G. Bankras ,  Theodorus G. M. Oosterlaken

IPC: H01L21/02 ,  C01B15/017 ,  H01L21/67

Abstract: In some embodiments, a system is disclosed for delivering hydrogen peroxide to a semiconductor processing chamber. The system includes a process canister for holding a H2O2/H2O mixture in a liquid state, an evaporator provided with an evaporator heater, a first feed line for feeding the liquid H2O2/H2O mixture to the evaporator, and a second feed line for feeding the evaporated H2O2/H2O mixture to the processing chamber, the second feed line provided with a second feed line heater. The evaporator heater is configured to heat the evaporator to a temperature lower than 120° C. and the second feed line heater is configured to heat the feed line to a temperature equal to or higher than the temperature of the evaporator.

公开(公告)号：US10199223B2

公开(公告)日：2019-02-05

申请号：US15413848

申请日：2017-01-24

Applicant: ASM IP Holding B.V.

Inventor： Dieter Pierreux ,  Werner Knaepen ,  Bert Jongbloed

IPC: H01L21/033

Abstract: An etch stop layer comprises a metal oxide comprising a metal selected from the group consisting of metals of Group 4 of the periodic table, metals of Group 5 of the periodic table, metals of Group 6 of the periodic table, and yttrium. The metal oxide forms exceptionally thin layers that are resistant to ashing and HF exposure. Subjecting the etch stop layer to both ashing and HF etch processes removes less than 0.3 nm of the thickness of the etch stop layer, and more preferably less than 0.25 nm. The etch stop layer may be thin and may have a thickness of about 0.5-2 nm. In some embodiments, the etch stop layer comprises tantalum oxide (TaO).

公开(公告)号：US20180033606A1

公开(公告)日：2018-02-01

申请号：US15222715

申请日：2016-07-28

Applicant: ASM IP Holding B.V.

Inventor： Viljami Pore ,  Werner Knaepen ,  Bert Jongbloed ,  Dieter Pierreux ,  Gido Van Der Star ,  Toshiya Suzuki

IPC: H01L21/02 ,  C23C16/50 ,  H01L21/762 ,  C23C16/455

CPC classification number: H01L21/0228 ,  C23C16/45525 ,  C23C16/50 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02211 ,  H01L21/02219 ,  H01L21/02274 ,  H01L21/76224

Abstract: There is provided a method of filling one or more gaps by providing the substrate in a reaction chamber and introducing a first reactant to the substrate with a first dose, thereby forming no more than about one monolayer by the first reactant on a first area; introducing a second reactant to the substrate with a second dose, thereby forming no more than about one monolayer by the second reactant on a second area of the surface, wherein the first and the second areas overlap in an overlap area where the first and second reactants react and leave an initially unreacted area where the first and the second areas do not overlap; and, introducing a third reactant to the substrate with a third dose, the third reactant reacting with the first or second reactant remaining on the initially unreacted area.

公开(公告)号：US09812320B1

公开(公告)日：2017-11-07

申请号：US15222738

申请日：2016-07-28

Applicant: ASM IP Holding B.V.

Inventor： Viljami Pore ,  Werner Knaepen ,  Bert Jongbloed ,  Dieter Pierreux ,  Steven R. A. Van Aerde ,  Suvi Haukka ,  Atsuki Fukuzawa ,  Hideaki Fukuda

IPC: H01L21/02 ,  C23C16/455 ,  C23C16/50 ,  H01J37/32 ,  H01L21/762

CPC classification number: H01L21/0228 ,  C23C16/045 ,  C23C16/402 ,  C23C16/45525 ,  C23C16/45534 ,  C23C16/45542 ,  C23C16/50 ,  H01J37/32009 ,  H01J2237/3321 ,  H01J2237/334 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02183 ,  H01L21/02211 ,  H01L21/02219 ,  H01L21/02274 ,  H01L21/02299 ,  H01L21/76224

Abstract: According to the invention there is provided a method of filling one or more gaps created during manufacturing of a feature on a substrate by providing a deposition method comprising; introducing a first reactant to the substrate with a first dose, thereby forming no more than about one monolayer by the first reactant; introducing a second reactant to the substrate with a second dose. The first reactant is introduced with a subsaturating first dose reaching only a top area of the surface of the one or more gaps and the second reactant is introduced with a saturating second dose reaching a bottom area of the surface of the one or more gaps. A third reactant may be provided to the substrate in the reaction chamber with a third dose, the third reactant reacting with at least one of the first and second reactant.

公开(公告)号：US09799509B2

公开(公告)日：2017-10-24

申请号：US14555429

申请日：2014-11-26

Applicant: ASM IP Holding B.V.

Inventor： Bert Jongbloed ,  Dieter Pierreux ,  Werner Knaepen

IPC: H01L21/02 ,  H01L21/308

CPC classification number: H01L21/02178 ,  H01L21/0228

Abstract: A process for depositing aluminum oxynitride (AlON) is disclosed. The process comprises subjecting a substrate to temporally separated exposures to an aluminum precursor and a nitrogen precursor to form an aluminum and nitrogen-containing compound on the substrate. The aluminum and nitrogen-containing compound is subsequently exposed to an oxygen precursor to form AlON. The temporally separated exposures to an aluminum precursor and a nitrogen precursor, and the subsequent exposure to an oxygen precursor together constitute an AlON deposition cycle. A plurality of AlON deposition cycles may be performed to deposit an AlON film of a desired thickness. The deposition may be performed in a batch process chamber, which may accommodate batches of 25 or more substrates. The deposition may be performed without exposure to plasma.

公开(公告)号：US20150287591A1

公开(公告)日：2015-10-08

申请号：US14686595

申请日：2015-04-14

Applicant: ASM IP HOLDING B.V.

Inventor： Viljami J. Pore ,  Yosuke Kimura ,  Kunitoshi Namba ,  Wataru Adachi ,  Hideaki Fukuda ,  Werner Knaepen ,  Dieter Pierreux ,  Bert Jongbloed

IPC: H01L21/02

CPC classification number: H01L21/02112 ,  C23C16/045 ,  C23C16/30 ,  C23C16/32 ,  C23C16/45523 ,  C23C16/45525 ,  C23C16/45531 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/0234 ,  H01L21/2254 ,  H01L21/31111

Abstract: Methods of depositing boron and carbon containing films are provided. In some embodiments, methods of depositing B, C films with desirable properties, such as conformality and etch rate, are provided. One or more boron and/or carbon containing precursors can be decomposed on a substrate at a temperature of less than about 400° C. One or more of the boron and carbon containing films can have a thickness of less than about 30 angstroms. Methods of doping a semiconductor substrate are provided. Doping a semiconductor substrate can include depositing a boron and carbon film over the semiconductor substrate by exposing the substrate to a vapor phase boron precursor at a process temperature of about 300° C. to about 450° C., where the boron precursor includes boron, carbon and hydrogen, and annealing the boron and carbon film at a temperature of about 800° C. to about 1200° C.

Abstract translation: 提供了沉积硼和碳的膜的方法。 在一些实施例中，提供了沉积具有所需性质（诸如保形性和蚀刻速率）的B，C膜的方法。 一种或多种含硼和/或碳的前体可以在低于约400℃的温度下在基材上分解。含硼和碳的一种或多种膜可以具有小于约30埃的厚度。 提供掺杂半导体衬底的方法。 掺杂半导体衬底可以包括通过在大约300℃至大约450℃的工艺温度下将衬底暴露于气相硼前体而在半导体衬底上沉积硼和碳膜，其中硼前体包括硼， 碳和氢，并在约800℃至约1200℃的温度下退火硼和碳膜。

公开(公告)号：US20250092520A1

公开(公告)日：2025-03-20

申请号：US18889183

申请日：2024-09-18

Applicant: ASM IP Holding B.V.

Inventor： Davide Proserpio ,  Dieter Pierreux ,  Theodorus G.M. Oosterlaken ,  Herbert Terhorst

IPC: C23C16/455 ,  C23C16/06 ,  C23C16/52

Abstract: In general, the various aspects of the technology of the present disclosure relate to semiconductor manufacturing apparatuses and processes which may comprise two or more accumulators connected in parallel to each other. The apparatus may have a solid-state precursor sublimator upstream from said two or more accumulators employed by the process.

公开(公告)号：US20230223255A1

公开(公告)日：2023-07-13

申请号：US18153272

申请日：2023-01-11

Applicant: ASM IP Holding, B.V.

Inventor： Steven Van Aerde ,  Wilco Verweij ,  Bert Jongbloed ,  Dieter Pierreux ,  Kelly Houben ,  Rami Khazaka ,  Frederick Aryeetey ,  Peter Westrom ,  Omar Elleuch ,  Caleb Miskin

IPC: H01L21/02 ,  C30B25/16 ,  C30B29/06 ,  C30B29/52 ,  C30B29/68

CPC classification number: H01L21/0257 ,  C30B25/165 ,  C30B29/06 ,  C30B29/52 ,  C30B29/68 ,  H01L21/0262 ,  H01L21/02532

Abstract: A method and a wafer processing furnace for forming an epitaxial stack on a plurality of substrates is provided. In a preferred embodiment, the method comprises providing the plurality of substrates to a process chamber. A plurality of deposition cycles is executed, thereby forming the epitaxial stack on the plurality of substrates. The epitaxial stack comprises a plurality of epitaxial pairs, wherein the epitaxial pairs each comprises a first epitaxial layer and a second epitaxial layer, the second epitaxial layer being different from the first epitaxial layer. Each deposition cycle comprises a first deposition pulse and a second deposition pulse. The first deposition pulse comprises a provision of a first reaction gas mixture to the process chamber, thereby forming the first epitaxial layer. The second deposition pulse comprises a provision of a second reaction gas mixture to the process chamber, thereby forming the second epitaxial layer. The first deposition pulse or the second deposition pulse further comprises a provision of a dopant precursor gas to the process chamber.

公开(公告)号：US11646204B2

公开(公告)日：2023-05-09

申请号：US17352555

申请日：2021-06-21

Applicant: ASM IP Holding B.V.

Inventor： Dieter Pierreux ,  Steven van Aerde ,  Bert Jongbloed ,  Kelly Houben ,  Werner Knaepen ,  Wilco Verweij

IPC: H01L21/02 ,  H01L27/11582

CPC classification number: H01L21/0262 ,  H01L21/02532 ,  H01L27/11582

Abstract: A method for forming layers with silicon is disclosed. The layers may be created by positioning a substrate within a processing chamber, heating the substrate to a first temperature between 300 and 500° C. and introducing a first precursor into the processing chamber to deposit a first layer. The substrate may be heated to a second temperature between 400 and 600° C.; and, a second precursor may be introduced into the processing chamber to deposit a second layer. The first and second precursor may comprise silicon atoms and the first precursor may have more silicon atoms per molecule than the second precursor.

公开(公告)号：US20230084173A1

公开(公告)日：2023-03-16

申请号：US17989875

申请日：2022-11-18

Applicant: ASM IP Holding B.V.

Inventor： Dieter Pierreux ,  Steven van Aerde ,  Bert Jongbloed

IPC: H01L21/768 ,  H01L27/11556 ,  H01L27/11582 ,  G11C5/06 ,  H01L23/538 ,  G11C5/02

Abstract: A method for forming a structure with a hole on a substrate is disclosed. The method may comprise: depositing a first structure on the substrate; etching a first part of the hole in the first structure; depositing a plug fill in the first part of the hole; depositing a second structure on top of the first structure; etching a second part of the hole substantially aligned with the first part of the hole in the second structure; and, etching the plug fill of the first part of the hole and thereby opening up the hole by dry etching. In this way 3-D NAND device may be provided.