公开(公告)号：US20160034023A1

公开(公告)日：2016-02-04

申请号：US14448096

申请日：2014-07-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Manish ARORA ,  Indrani Paul ,  Yasuko Eckert ,  Joseph L. Greathouse ,  Srilatha Manne

IPC: G06F1/32 ,  G06F12/08

CPC classification number: G06F1/3275 ,  G06F1/3206 ,  G06F12/0811 ,  G06F12/0862 ,  G06F2212/1016 ,  G06F2212/502 ,  Y02D10/14

Abstract: A system may determine that a processor has powered up. The system may determine a first prefetching policy based on determining that the processor has powered up. The system may fetch information, from a main memory and for storage by a cache associated with the processor, using the first prefetching policy. The system may determine, after fetching information using the first prefetching policy, to apply a second prefetching policy that is different than the first prefetching policy. The system may fetch information, from the main memory and for storage by the cache, using the second prefetching policy.

Abstract translation: 系统可以确定处理器已经通电。 该系统可以基于确定处理器通电来确定第一预取策略。 系统可以使用第一预取策略从主存储器获取信息，并且由与处理器相关联的高速缓存存储信息。 在使用第一预取策略获取信息之后，系统可以确定应用与第一预取策略不同的第二预取策略。 系统可以使用第二预取策略从主存储器获取信息并由高速缓存存储。

公开(公告)号：US09223383B2

公开(公告)日：2015-12-29

申请号：US13724271

申请日：2012-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Srilatha Manne ,  Rajagopalan Desikan ,  Sanjay Pant ,  Youngtaek Kim

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/3243 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/172 ,  Y02D50/20

Abstract: A multi-core data processor includes multiple data processor cores and a power controller. Each data processor core has a first input for receiving a clock signal, a second input for receiving a power supply voltage, and an output for providing an idle signal. The power controller is coupled to each of the data processor cores for providing the clock signal and the power supply voltage to each of the data processor cores. The power controller provides at least one of the clock signal and the power supply voltage to an active one of the data processor cores in dependence on a number of idle signals received from the data processor cores.

Abstract translation: 多核数据处理器包括多个数据处理器内核和电源控制器。 每个数据处理器内核具有用于接收时钟信号的第一输入端，用于接收电源电压的第二输入端和用于提供空闲信号的输出端。 功率控制器耦合到每个数据处理器核心，用于向每个数据处理器核提供时钟信号和电源电压。 功率控制器根据从数据处理器核心接收到的空闲信号的数量，向时钟信号和电源电压提供至少一个数据处理器核心中的一个。

公开(公告)号：US20150185801A1

公开(公告)日：2015-07-02

申请号：US14146591

申请日：2014-01-02

Applicant: Advanced Micro Devices, Inc.

Inventor： Manish Arora ,  Indrani Paul ,  Yasuko Eckert ,  Nuwan S. Jayasena ,  Srilatha Manne ,  Madhu Saravana Sibi Govindan ,  William L. Bircher

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3225 ,  Y02D10/171 ,  Y02D50/20

Abstract: Power gating decisions can be made based on measures of cache dirtiness. Analyzer logic can selectively power gate a component of a processor system based on a cache dirtiness of one or more caches associated with the component. The analyzer logic may power gate the component when the cache dirtiness exceeds a threshold and may maintains the component in an idle state when the cache dirtiness does not exceed the threshold. Idle time prediction logic may be used to predict a duration of an idle time of the component. The analyzer logic may then selectively power gates the component based on the cache dirtiness and the predicted idle time.

Abstract translation: 电源选通决定可以基于缓存污垢的测量。 分析器逻辑可以基于与组件相关联的一个或多个高速缓存的高速缓存污垢来选择性地加电处理系统的组件。 当高速缓存污物超过阈值时，分析器逻辑可以对组件供电，并且当高速缓存污垢不超过阈值时，分析器逻辑可以维持组件处于空闲状态。 空闲时间预测逻辑可以用于预测组件的空闲时间的持续时间。 然后，分析器逻辑可以基于高速缓存污物和预测的空闲时间选择性地对组件进行加电。

公开(公告)号：US20150067356A1

公开(公告)日：2015-03-05

申请号：US14015369

申请日：2013-08-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Vignesh Trichy Ravi ,  Manish Arora ,  William Brantley ,  Srilatha Manne ,  Indrani Paul ,  Michael Schulte

IPC: G06F1/26

CPC classification number: G06F1/324 ,  G06F1/3287 ,  G06F1/329 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/24

Abstract: A data processing system includes a plurality of processor resources, a manager, and a power distributor. Each of the plurality of data processor cores is operable at a selected one of a plurality of performance states. The manager assigns each of a plurality of program elements to one of the plurality of processor resources, and synchronizing the program elements using barriers. The power distributor is coupled to the manager and to the plurality of processor resources, and assigns a performance state to each of the plurality of processor resources within an overall power budget, and in response to detecting that a program element assigned to a first processor resource is at a barrier, increases the performance state of a second processor resource that is not at the barrier within the overall power budget.

Abstract translation: 数据处理系统包括多个处理器资源，管理器和功率分配器。 多个数据处理器核心中的每一个可操作在多个执行状态中的选定的一个。 管理器将多个程序元素中的每一个分配给多个处理器资源中的一个，并且使用屏障同步程序元素。 功率分配器耦合到管理器和多个处理器资源，并且在总功率预算内为多个处理器资源中的每一个分配一个性能状态，并且响应于检测到分配给第一处理器资源的程序元件 处于障碍之下，增加在整个功率预算范围内不处于障碍的第二处理器资源的性能状态。

公开(公告)号：US20140181556A1

公开(公告)日：2014-06-26

申请号：US13724599

申请日：2012-12-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Yasuko Eckert ,  Srilatha Manne ,  William L. Bircher ,  Mahdu S.S. Govindan ,  Michael J. Schulte ,  Manish Arora

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/172

Abstract: A method and apparatus for exiting a low power state based on a prior prediction is disclosed. An integrated circuit (IC) includes a functional unit configured to, during operation, cycle between intervals of an active state and intervals of an idle state. The IC also include a power management unit configured to place the functional unit in a low power state responsive to the functional unit entering the idle state. The power management unit is further configured to preemptively cause the functional unit to exit the low power state at a predetermined time after entering the low power. The predetermined time is based on a prediction of idle state duration made prior to entering the low power state. The prediction may be generated by a prediction unit, based on a history of durations of intervals in which the functional unit was in the idle state.

Abstract translation: 公开了一种基于先前预测退出低功率状态的方法和装置。 集成电路（IC）包括功能单元，其被配置为在操作期间在活动状态的间隔和空闲状态的间隔之间循环。 IC还包括电源管理单元，其被配置为响应于功能单元进入空闲状态而将功能单元置于低功率状态。 电源管理单元还被配置为在进入低功率之后的预定时间，预先使功能单元退出低功率状态。 预定时间基于在进入低功率状态之前进行的空闲状态持续时间的预测。 预测可以由预测单元基于功能单元处于空闲状态的间隔的持续时间的历史来生成。

公开(公告)号：US20140181554A1

公开(公告)日：2014-06-26

申请号：US13724133

申请日：2012-12-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Srilatha Manne ,  Sanjay Pant ,  Youngtaek Kim ,  Michael J. Schulte

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3243 ,  Y02D10/152

Abstract: A multi-core data processor includes multiple data processor cores and a circuit. The multiple data processor cores each include a power state controller having a first input for receiving an idle signal, a second input for receiving a release signal, a third input for receiving a control signal, and an output for providing a current power state. In response to the idle signal, the power state controller causes a corresponding data processor core to enter an idle state. In response to the release signal, the power state controller changes the current power state from the idle state to an active state in dependence on the control signal. The circuit is coupled to each of the multiple data processor cores for providing the control signal in response to current power states in the multiple data processor cores.

Abstract translation: 多核数据处理器包括多个数据处理器核心和一个电路。 多个数据处理器核心各自包括具有用于接收空闲信号的第一输入的功率状态控制器，用于接收释放信号的第二输入，用于接收控制信号的第三输入和用于提供当前功率状态的输出。 响应于空闲信号，电源状态控制器使相应的数据处理器核进入空闲状态。 响应于释放信号，功率状态控制器根据控制信号将当前功率状态从空闲状态改变到活动状态。 电路耦合到多个数据处理器核心中的每一个，以响应于多个数据处理器核心中的当前功率状态来提供控制信号。

公开(公告)号：US20140181553A1

公开(公告)日：2014-06-26

申请号：US13723868

申请日：2012-12-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Yasuko Eckert ,  Srilatha Manne ,  William L. Bircher ,  Mahdu S.S. Govindan ,  Michael J. Schulte

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3206 ,  G06F1/3237 ,  G06F1/3243 ,  G06F1/329 ,  Y02D10/128 ,  Y02D10/152 ,  Y02D10/24 ,  Y02D50/20

Abstract: A method and apparatus for idle phase prediction in integrated circuits is disclosed. In one embodiment, an integrated circuit (IC) includes a functional unit configured to cycle between intervals of an active state and an idle state. The IC further includes a prediction unit configured to record a history of idle state durations for a plurality of intervals of the idle state. Based on the history of idle state durations, the prediction unit is configured to generate a prediction of the duration of the next interval of the idle state. The prediction may be used by a power management unit to, among other uses, determine whether to place the functional unit in a low power (e.g., sleep) state.

Abstract translation: 公开了一种用于集成电路中的空闲相位预测的方法和装置。 在一个实施例中，集成电路（IC）包括被配置为在活动状态的间隔和空闲状态之间循环的功能单元。 IC还包括：预测单元，被配置为在空闲状态的多个间隔中记录空闲状态持续时间的历史。 基于空闲状态持续时间的历史，预测单元被配置为生成空闲状态的下一个间隔的持续时间的预测。 电力管理单元可以使用该预测，除了其他用途之外，确定是否将功能单元置于低功率（例如睡眠）状态。

公开(公告)号：US20140149772A1

公开(公告)日：2014-05-29

申请号：US14075645

申请日：2013-11-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Manish Arora ,  Nuwan S. Jayasena ,  Yasuko Eckert ,  Madhu Saravana Sibi Govindan ,  William L. Bircher ,  Michael J. Schulte ,  Srilatha Manne

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/206

Abstract: The described embodiments include a computing device with one or more entities (processor cores, processors, etc.). In some embodiments, during operation, a thermal power management unit in the computing device uses a linear prediction to compute a predicted duration of a next idle period for an entity based on the duration of one or more previous idle periods for the entity. Based on the predicted duration of the next idle period, the thermal power management unit configures the entity to operate in a corresponding idle state.

Abstract translation: 所描述的实施例包括具有一个或多个实体（处理器核心，处理器等）的计算设备。 在一些实施例中，在操作期间，计算设备中的热功率管理单元使用线性预测来基于实体的一个或多个先前空闲周期的持续时间来计算实体的下一个空闲周期的预测持续时间。 基于下一个空闲周期的预测持续时间，热功率管理单元将实体配置为在相应的空闲状态下工作。

公开(公告)号：US20140143499A1

公开(公告)日：2014-05-22

申请号：US13945659

申请日：2013-07-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Lena E. Olson ,  Yasuko Eckert ,  Vilas K. Sridharan ,  James M. O'Connor ,  Mark D. Hill ,  Srilatha Manne

IPC: G06F12/12 ,  G06F12/08

CPC classification number: G06F12/0802 ,  G06F12/0848 ,  G06F12/0862 ,  G06F12/0864 ,  G06F12/0875 ,  G06F12/123 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/451 ,  G06F2212/502 ,  G06F2212/601 ,  G06F2212/6032 ,  G06F2212/6082 ,  Y02D10/13

Abstract: A method of way prediction for a data cache having a plurality of ways is provided. Responsive to an instruction to access a stack data block, the method accesses identifying information associated with a plurality of most recently accessed ways of a data cache to determine whether the stack data block resides in one of the plurality of most recently accessed ways of the data cache, wherein the identifying information is accessed from a subset of an array of identifying information corresponding to the plurality of most recently accessed ways; and when the stack data block resides in one of the plurality of most recently accessed ways of the data cache, the method accesses the stack data block from the data cache.

Abstract translation: 提供了一种具有多种方式的数据高速缓存的方式预测方法。 响应于访问堆栈数据块的指令，该方法访问与数据高速缓存的多个最近访问的方式相关联的识别信息，以确定堆栈数据块是否位于数据的多个最近访问的方式之一 高速缓存，其中从与多个最近访问的方式对应的识别信息的数组的子集中访问所述识别信息; 并且当堆栈数据块驻留在数据高速缓存的多个最近被访问的方式之一时，该方法从数据高速缓存访​​问堆栈数据块。

公开(公告)号：US20140143492A1

公开(公告)日：2014-05-22

申请号：US14018562

申请日：2013-09-05

Applicant: Advanced Micro Devices, Inc.

Inventor： Yasuko Eckert ,  Lena E. Olson ,  Srilatha Manne ,  James M. O'Connor

IPC: G06F12/08

CPC classification number: G06F12/0802 ,  G06F9/3834 ,  G06F9/3838 ,  G06F12/0848 ,  G06F12/0862 ,  G06F12/0864 ,  G06F12/0875 ,  G06F12/123 ,  G06F2212/1016 ,  G06F2212/451 ,  G06F2212/502 ,  G06F2212/6022 ,  G06F2212/6032 ,  Y02D10/13

Abstract: The described embodiments include a core that uses predictions for store-to-load forwarding. In the described embodiments, the core comprises a load-store unit, a store buffer, and a prediction mechanism. During operation, the prediction mechanism generates a prediction that a load will be satisfied using data forwarded from the store buffer because the load loads data from a memory location in a stack. Based on the prediction, the load-store unit first sends a request for the data to the store buffer in an attempt to satisfy the load using data forwarded from the store buffer. If data is returned from the store buffer, the load is satisfied using the data. However, if the attempt to satisfy the load using data forwarded from the store buffer is unsuccessful, the load-store unit then separately sends a request for the data to a cache to satisfy the load.

Abstract translation: 所描述的实施例包括使用对存储到负载转发的预测的核心。 在所描述的实施例中，核心包括加载存储单元，存储缓冲器和预测机制。 在运行期间，预测机制产生一个预测，即使用从存储缓冲器转发的数据来满足负载，因为负载从栈中的存储器位置加载数据。 基于该预测，加载存储单元首先向存储缓冲器发送对数据的请求，以尝试使用从存储缓冲器转发的数据来满足负载。 如果从存储缓冲区返回数据，则使用该数据来满足负载。 然而，如果使用从存储缓冲器转发的数据来满足负载的尝试不成功，则加载存储单元然后分别向缓存发送用于满足负载的数据请求。