公开(公告)号：US07236024B2

公开(公告)日：2007-06-26

申请号：US11239943

申请日：2005-09-30

申请人： Yunteng Huang ,  Ligang Zhang ,  Axel Thomsen

发明人： Yunteng Huang ,  Ligang Zhang ,  Axel Thomsen

IPC分类号： H03L7/06

CPC分类号： G06F7/68 ,  H03L7/183 ,  H03L7/23

摘要： A PLL function may be implemented as a dual-loop structure having a first PLL circuit which generates an intermediate signal from the reference signal, and a second PLL circuit which generates an output signal from the intermediate signal. The intermediate signal frequency is preferably chosen at a value in which potential interference signals do not have much energy. The first loop preferably has low bandwidth to provide good input jitter attenuation, while second loop preferably has higher bandwidth to reduce phase noise of the output signal. The circuit preferably provides for a choice of several different intermediate frequencies to allow use where different intermediate frequencies may exist in each system. Moreover, in a system having two such dual-loop PLL circuits, each can be configured with a different intermediate frequency, so that interference from one to the other is reduced.

摘要翻译： PLL功能可以实现为具有从参考信号产生中间信号的第一PLL电路的双回路结构，以及从中间信号产生输出信号的第二PLL电路。 中间信号频率优选地被选择为其中潜在的干扰信号没有太多能量的值。 第一环路优选具有低带宽以提供良好的输入抖动衰减，而第二环路优选地具有较高带宽以减少输出信号的相位噪声。 该电路优选地提供几种不同中频的选择，以允许在每个系统中可能存在不同中频的应用。 此外，在具有两个这样的双回路PLL电路的系统中，每个都可以配置有不同的中频，从而减少了从一个到另一个的干扰。

公开(公告)号：US20070139088A1

公开(公告)日：2007-06-21

申请号：US11680026

申请日：2007-02-28

申请人： Akhil Garlapati ,  Lizhong Sun ,  Douglas Pastorello ,  Richard Juhn ,  Axel Thomsen

发明人： Akhil Garlapati ,  Lizhong Sun ,  Douglas Pastorello ,  Richard Juhn ,  Axel Thomsen

IPC分类号： H03K23/00

CPC分类号： H03K23/66 ,  H03K21/10 ,  H03L7/0805 ,  H03L7/087 ,  H03L7/091 ,  H03L7/093 ,  H03L7/193 ,  H03L7/1974 ,  H03L7/1976

摘要： In at least one embodiment of the invention, a method for dividing a first signal having a first frequency by a divide ratio to generate a lower frequency signal includes generating a first plurality of signals having a common frequency, a first pulse width, and different phases. The first plurality of signals is based, at least in part, on at least one signal having a second pulse width. The first pulse width is selected from a plurality of pulse widths based, at least in part, on the divide ratio. The method includes sequentially selecting individual pulses of the first plurality of signals as an output signal of a select circuit to generate an output signal having a frequency lower than the first frequency.

摘要翻译： 在本发明的至少一个实施例中，一种用于将具有第一频率的第一信号除以分频比以产生较低频率信号的方法包括产生具有共同频率，第一脉冲宽度和不同相位的第一多个信号 。 第一组多个信号至少部分地基于具有第二脉冲宽度的至少一个信号。 至少部分地基于分频比，从多个脉冲宽度中选择第一脉冲宽度。 该方法包括顺序选择第一多个信号中的各个脉冲作为选择电路的输出信号，以产生具有低于第一频率的频率的输出信号。

公开(公告)号：US07187241B2

公开(公告)日：2007-03-06

申请号：US10675543

申请日：2003-09-30

申请人： Jerrell Hein ,  Axel Thomsen

发明人： Jerrell Hein ,  Axel Thomsen

IPC分类号： H03L7/00

CPC分类号： H03L1/022 ,  H03L1/026 ,  H03L7/095 ,  H03L7/0992 ,  H03L7/1976 ,  H03L7/235 ,  H03L2207/50

摘要： A clock device having a resonating device such as a crystal of SAW supplying a controllable oscillator such as a digitally controlled oscillator is calibrated by supplying a calibration clock. A phase-locked loop is utilized to generate one or more correction factors causing the PLL to lock to the calibration clock. The one or more correction factors are then stored in non-volatile memory.

摘要翻译： 通过提供校准时钟来校准具有诸如数字控制振荡器等可控振荡器的SAW的晶体谐振装置的时钟装置。 利用锁相环产生一个或多个校正因子，使PLL锁定到校准时钟。 然后将一个或多个校正因子存储在非易失性存储器中。

公开(公告)号：US06614285B2

公开(公告)日：2003-09-02

申请号：US09054521

申请日：1998-04-03

申请人： Wai Laing Lee ,  Dan Kasha ,  Axel Thomsen

发明人： Wai Laing Lee ,  Dan Kasha ,  Axel Thomsen

IPC分类号： G06G7186

CPC分类号： G06G7/1865

摘要： Power available to an integrator circuit is controlled so that relatively high power is provided during one phase of operation, such as during an interval when slewing in a device is expected and relatively low power is provided during another phase. In one implementation, increased power is provided by switching in parallel current mirrors when power demands are expected to be high, whether or not high power is actually needed in a particular interval. The techniques are particularly useful when applied to clocked integrator circuits.

摘要翻译： 对集成电路可用的功率进行控制，使得在一个操作阶段期间提供相对较高的功率，例如在期望设备中回转的间隔期间，并且在另一阶段期间提供相对较低的功率。 在一个实施方式中，当功率需求预期为高时，无论在特定间隔中是否实际需要高功率，通过切换并联电流镜来提供功率增加。 当应用于时钟积分器电路时，这些技术特别有用。

公开(公告)号：US06445791B1

公开(公告)日：2002-09-03

申请号：US09370404

申请日：1999-08-09

申请人： Robert Thomas Grisamore ,  Kartika Putra Prihadi ,  Eric Swanson ,  Karl Nordling ,  Axel Thomsen

发明人： Robert Thomas Grisamore ,  Kartika Putra Prihadi ,  Eric Swanson ,  Karl Nordling ,  Axel Thomsen

IPC分类号： H04M100

CPC分类号： H04L25/085 ,  H04L25/0266

摘要： An interface for coupling a modem port with a transmission line includes a hybrid converter having a variable gain amplifier coupling a transmit path of a first differential polarity and a received path of a second differential polarity.

摘要翻译： 用于将调制解调器端口与传输线耦合的接口包括具有耦合第一差分极性的发送路径和第二差分极性的接收路径的可变增益放大器的混合转换器。

公开(公告)号：US06369745B1

公开(公告)日：2002-04-09

申请号：US09054542

申请日：1998-04-03

申请人： Wai Laing Lee ,  Dan Kasha ,  Axel Thomsen

发明人： Wai Laing Lee ,  Dan Kasha ,  Axel Thomsen

IPC分类号： H03M150

CPC分类号： H03M3/32 ,  H03M3/374 ,  H03M3/43 ,  H03M3/448 ,  H03M3/452

摘要： Power available to a delta sigma modulator is controlled so that relatively high power is provided during one phase of operation, such as during an interval when slewing in a device is expected and relatively low power is provided during another phase. In one implementation, increased power is provided by switching in parallel current mirrors when power demands are expected to be high, whether or not high power is actually needed in a particular interval. A large step size is selected to reduce power corruption and feedback coefficients are optimized for low power by running at a higher oversampling rate than required by signal to quantization noise requirements.

摘要翻译： 控制对ΔΣ调制器的可用功率，使得在一个操作阶段期间提供相对较高的功率，例如在期望设备中回转的间隔期间，并且在另一阶段期间提供相对较低的功率。 在一个实施方式中，当功率需求预期为高时，无论在特定间隔中是否实际需要高功率，通过切换并联电流镜来提供功率增加。 选择大的步长以减少功率损耗，并且通过以比信号对量化噪声要求所要求的更高的过采样速率运行来为低功率优化反馈系数。

公开(公告)号：US6163286A

公开(公告)日：2000-12-19

申请号：US89496

申请日：1998-06-02

申请人： Wai Laing Lee ,  Axel Thomsen ,  Lei Wang ,  Dan Kasha

发明人： Wai Laing Lee ,  Axel Thomsen ,  Lei Wang ,  Dan Kasha

IPC分类号： G01R31/28 ,  H03M3/04 ,  H03M1/66

CPC分类号： G01R31/2841

摘要： A high performance test signal generator uses a digital to analog converter which converts an N-bit digital signal, such as provided by a computer waveform generator or by a CDROM into an M-bit upsampled digital signal. The M-bit digital signal is applied to an M-bit digital to analog converter to produce an analog output signal. The analog output signal is sampled and fed back across, the discrete time/continuous time interface to the input of the conversion circuit. The test signal generator has very low power consumption yet meets very strict noise and linearity requirements. The test signal generator can be used for testing seismic sensors such as geophones or hydrophones.

摘要翻译： 高性能测试信号发生器使用数模转换器，其将诸如由计算机波形发生器或CDROM提供的N位数字信号转换为M位上采样的数字信号。 M位数字信号被施加到M位数模转换器以产生模拟输出信号。 模拟输出信号被采样并反馈到离散的时间/连续时间接口到转换电路的输入端。 测试信号发生器具有非常低的功耗，但满足非常严格的噪声和线性要求。 测试信号发生器可用于测试地震检波器，如地震检波器或水听器。

公开(公告)号：US08681026B2

公开(公告)日：2014-03-25

申请号：US13408173

申请日：2012-02-29

申请人： Jinwen Xiao ,  Pavel Konecny ,  Axel Thomsen ,  Ka Y. Leung

发明人： Jinwen Xiao ,  Pavel Konecny ,  Axel Thomsen ,  Ka Y. Leung

IPC分类号： H03M1/06

CPC分类号： H03M1/1047 ,  H03M1/745 ,  H03M1/785

摘要： An input digital signal is converted to an analog signal using a main digital to analog converter (DAC) and a sub DAC. An offset value is subtracted from the input digital signal to generate an offset adjusted digital signal. The main DAC converts the offset adjusted digital signal to a first analog signal. A second digital signal is generated based on the offset value and a correction factor determined, at least in part, during calibration of the main DAC. The sub DAC converts the second digital to a second analog signal, which when combined with the first analog signal, provides an analog representation of the input digital signal.

摘要翻译： 使用主数模转换器（DAC）和子DAC将输入数字信号转换为模拟信号。 从输入数字信号中减去偏移值，以生成偏移调整数字信号。 主DAC将偏移调整后的数字信号转换为第一个模拟信号。 基于偏移值和至少部分地在主DAC的校准期间确定的校正因子来生成第二数字信号。 子DAC将第二数字转换为第二模拟信号，当与第一模拟信号组合时，该模拟信号提供输入数字信号的模拟表示。

公开(公告)号：US20130082740A1

公开(公告)日：2013-04-04

申请号：US13249349

申请日：2011-09-30

申请人： Axel Thomsen

发明人： Axel Thomsen

IPC分类号： H03K5/00

CPC分类号： H03K5/00 ,  H04L27/0002

摘要： An integrated circuit includes a configurable interface. The configurable interface includes an operational amplifier, a programmable gain amplifier, an analog-to-digital converter and a first select circuit. The first select circuit is configured to selectively couple the operational amplifier to the analog-to-digital converter in response to a first control signal. The first select circuit is further configured to selectively couple the programmable gain amplifier to the analog-to-digital converter in response to the first control signal.

摘要翻译： 集成电路包括可配置接口。 可配置接口包括运算放大器，可编程增益放大器，模数转换器和第一选择电路。 第一选择电路被配置为响应于第一控制信号选择性地将运算放大器耦合到模拟 - 数字转换器。 第一选择电路还被配置为响应于第一控制信号选择性地将可编程增益放大器耦合到模拟 - 数字转换器。

公开(公告)号：US08198951B2

公开(公告)日：2012-06-12

申请号：US12414379

申请日：2009-03-30

申请人： Zhiwei Dong ,  Shouli Yan ,  Axel Thomsen ,  William W. K. Tang ,  Ka Y. Leung

发明人： Zhiwei Dong ,  Shouli Yan ,  Axel Thomsen ,  William W. K. Tang ,  Ka Y. Leung

IPC分类号： H04B3/28 ,  H01P5/02

CPC分类号： H04B3/02 ,  H01L23/48 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49575 ,  H01L23/66 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L2223/6611 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49176 ,  H01L2224/85399 ,  H01L2225/06506 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H03K5/135 ,  H03K17/689 ,  H03M9/00 ,  H04L5/14 ,  H04L25/0266 ,  H04L25/0268 ,  H04L25/0272 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

摘要： An integrated circuit having voltage isolation capabilities includes a plurality of communications channels for transceiving data from the integrated circuit. Each of the communications channel includes capacitive isolation circuitry located in conductive layers of the integrated circuit for providing a high voltage isolation link. The capacitive isolation circuitry distributes a first portion of a high voltage isolation signal across a first group of capacitors on a first link and a second link in the capacitive isolation circuitry and distributes a second portion of the high voltage isolation signal across a second group of capacitors in the first link and the second link in the capacitive isolation circuitry. A differential receiver on each of the plurality of communications channels receives the data on the first link and the second link. A differential transmitter on each of the plurality of communications channels transmits the data on the first link at a selected one of a first phase and a second phase and for transmitting the data on the second link at the selected one of the first phase and the second phase. The second phase is 180 degrees out of phase with the first phase. Each of the differential transmitters controls the selection of the first phase and the second phase on each of the first link and the second link such that only the first phase or the second phase is cross coupled onto a selected communications channel from adjacent communications channels.

摘要翻译： 具有电压隔离能力的集成电路包括用于从集成电路收发数据的多个通信信道。 每个通信信道包括位于集成电路的导电层中的电容隔离电路，用于提供高电压隔离链路。 电容隔离电路在电容隔离电路中的第一链路和第二链路上跨第一组电容器分配高电压隔离信号的第一部分，并且将第二部分高电压隔离信号分配到第二组电容器 在电容隔离电路中的第一链路和第二链路中。 多个通信信道中的每一个上的差分接收机在第一链路和第二链路上接收数据。 多个通信信道中的每一个上的差分发射机以第一相位和第二相位中的所选择的一个在第一链路上发送数据，并且用于在第一和第二相位中选定的一个的第二链路上发送数据 相。 第二阶段与第一阶段相差180度。 每个差分发射机控制在第一链路和第二链路中的每一个上的第一相位和第二相位的选择，使得只有第一相位或第二相位相互耦合到来自相邻通信信道的所选择的通信信道上。