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公开(公告)号：US20120326241A1
公开(公告)日：2012-12-27
申请号：US13603572
申请日：2012-09-05
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/823807 , H01L21/28518 , H01L21/76805 , H01L21/76829 , H01L21/76895 , H01L21/823814 , H01L21/823871 , H01L23/485 , H01L29/165 , H01L29/41766 , H01L29/665 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7843 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： Contact via holes are etched in a dielectric material layer overlying a semiconductor layer to expose the topmost surface of the semiconductor layer. The contact via holes are extended into the semiconductor material layer by continuing to etch the semiconductor layer so that a trench having semiconductor sidewalls is formed in the semiconductor material layer. A metal layer is deposited over the dielectric material layer and the sidewalls and bottom surface of the trench. Upon an anneal at an elevated temperature, a metal semiconductor alloy region is formed, which includes a top metal semiconductor alloy portion that includes a cavity therein and a bottom metal semiconductor alloy portion that underlies the cavity and including a horizontal portion. A metal contact via is formed within the cavity so that the top metal semiconductor alloy portion laterally surrounds a bottom portion of a bottom portion of the metal contact via.
摘要翻译： 在覆盖半导体层的电介质材料层中蚀刻接触孔，以露出半导体层的最上表面。 接触通孔延伸到半导体材料层中，继续蚀刻半导体层，使得在半导体材料层中形成具有半导体侧壁的沟槽。 在电介质材料层和沟槽的侧壁和底表面上沉积金属层。 在高温退火时，形成金属半导体合金区域，其包括顶部金属半导体合金部分，其中包括空腔，底部金属半导体合金部分位于空腔下方并包括水平部分。 金属接触通孔形成在空腔内，使得顶部金属半导体合金部分横向地围绕金属接触通孔的底部的底部。
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公开(公告)号：US08309447B2
公开(公告)日：2012-11-13
申请号：US12855273
申请日：2010-08-12
申请人： Kangguo Cheng , Bruce B. Doris , Lisa F. Edge , Balasubramanian S. Haran , Hemanth Jagannathan , Ali Khakifirooz , Vamsi K. Paruchuri
发明人： Kangguo Cheng , Bruce B. Doris , Lisa F. Edge , Balasubramanian S. Haran , Hemanth Jagannathan , Ali Khakifirooz , Vamsi K. Paruchuri
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/823857 , H01L21/823462 , H01L21/823481 , H01L21/823878
摘要： A method to achieve multiple threshold voltage (Vt) devices on the same semiconductor chip is disclosed. The method provides different threshold voltage devices using threshold voltage adjusting materials and a subsequent drive in anneal instead of directly doping the channel. As such, the method of the present disclosure avoids short channel penalties. Additionally, no ground plane/back gates are utilized in the present application thereby the method of the present disclosure can be easily integrated into current complementary metal oxide semiconductor (CMOS) processing technology.
摘要翻译： 公开了在同一半导体芯片上实现多个阈值电压（Vt）器件的方法。 该方法提供使用阈值电压调节材料的不同阈值电压器件，以及随后的退火驱动而不是直接掺杂通道。 因此，本公开的方法避免了短信道惩罚。 此外，在本申请中没有使用接地平面/后门，因此本公开的方法可以容易地集成到电流互补金属氧化物半导体（CMOS）处理技术中。
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43.发明授权Integration of multiple threshold voltage devices for complementary metal oxide semiconductor using full metal gate 有权使用全金属栅极集成多个阈值电压器件用于互补金属氧化物半导体公开(公告)号：US09093558B2
公开(公告)日：2015-07-28
申请号：US13594772
申请日：2012-08-24
IPC分类号： H01L21/8238 , H01L21/28 , H01L29/49 , H01L29/51
CPC分类号： H01L27/0922 , H01L21/28088 , H01L21/823835 , H01L21/823842 , H01L27/088 , H01L29/45 , H01L29/4966 , H01L29/517
摘要： A substrate is provided, having formed thereon a first region and a second region of a complementary type to the first region. A gate dielectric is deposited over the substrate, and a first full metal gate stack is deposited over the gate dielectric. The first full metal gate stack is removed over the first region to produce a resulting structure. Over the resulting structure, a second full metal gate stack is deposited, in contact with the gate dielectric over the first region. The first and second full metal gate stacks are encapsulated.
摘要翻译： 提供了基板，其上形成有与第一区域互补的第一区域和第二区域。 在衬底上沉积栅极电介质，并且在栅极电介质上沉积第一全金属栅极堆叠。 在第一区域上去除第一个全金属栅极叠层，以产生结果。 在所得到的结构上，在第一区域上沉积与栅极电介质接触的第二全金属栅极堆叠。 第一和第二全金属栅极堆叠被封装。
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公开(公告)号：US09087741B2
公开(公告)日：2015-07-21
申请号：US13179990
申请日：2011-07-11
IPC分类号： H01L27/12 , H01L21/84 , H01L21/8238
CPC分类号： H01L27/1203 , H01L21/0217 , H01L21/02178 , H01L21/02181 , H01L21/02189 , H01L21/02529 , H01L21/02532 , H01L21/0257 , H01L21/02592 , H01L21/0332 , H01L21/283 , H01L21/30604 , H01L21/31111 , H01L21/32053 , H01L21/324 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L21/823878 , H01L21/84 , H01L27/0922 , H01L29/0653 , H01L29/16 , H01L29/1608 , H01L29/161 , H01L29/167 , H01L29/41783 , H01L29/45 , H01L29/665 , H01L29/6656
摘要： An apparatus and a method for creating a CMOS with a dual raised source and drain for NMOS and PMOS. The spacers on both stack gates are of equal thickness. In this method, a first insulating layer is formed on the surface. The first region is then masked while the other region has the first layer etched away and has an epitaxial source and drain grown on the region. A second layer is formed to all exposed surfaces. The second region is then masked while the first region is etched away. The epitaxial source and drain is formed on the first region. The second region can also be masked by adding a thin layer of undoped silicon and then oxidize it. Another way to mask the second region is to use a hard mask. Another way to form the second source and drain is to use amorphous material.
摘要翻译： 一种用于产生具有用于NMOS和PMOS的双凸起源极和漏极的CMOS的装置和方法。 两个堆叠门上的间隔物的厚度相同。 在该方法中，在表面上形成第一绝缘层。 然后第一区域被掩蔽，而另一区域具有蚀刻掉的第一层，并且在该区域上生长外延源和漏极。 第二层形成于所有暴露的表面。 然后在第一区域被蚀刻掉的同时掩蔽第二区域。 外延源极和漏极形成在第一区域上。 第二区域也可以通过加入一薄层未掺杂的硅然后氧化来掩蔽。 掩盖第二个区域的另一种方法是使用硬面罩。 形成第二源和漏极的另一种方法是使用无定形材料。
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公开(公告)号：US08664050B2
公开(公告)日：2014-03-04
申请号：US13424447
申请日：2012-03-20
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0653 , H01L21/76224 , H01L21/84 , H01L29/66545
摘要： A structure and method to improve ETSOI MOSFET devices. A wafer is provided including regions with at least a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer. The regions are separated by a STI which extends at least partially into the second semiconductor layer and is partially filled with a dielectric. A gate structure is formed over the first semiconductor layer and during the wet cleans involved, the STI divot erodes until it is at a level below the oxide layer. Another dielectric layer is deposited over the device and a hole is etched to reach source and drain regions. The hole is not fully landed, extending at least partially into the STI, and an insulating material is deposited in said hole.
摘要翻译： 改进ETSOI MOSFET器件的结构和方法。 提供晶片，其包括具有覆盖在第二半导体层上的氧化物层的至少第一半导体层的区域。 这些区域由至少部分地延伸到第二半导体层中并且部分地填充有电介质的STI分开。 在第一半导体层上形成栅极结构，并且在涉及的湿清洗期间，STI纹路侵蚀直到其处于低于氧化物层的水平。 在器件上沉积另一个介电层，并蚀刻一个孔以到达源极和漏极区。 孔不完全落地，至少部分地延伸到STI中，并且绝缘材料沉积在所述孔中。
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46.发明申请INTEGRATION OF MULTIPLE THRESHOLD VOLTAGE DEVICES FOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR USING FULL METAL GATE 有权使用全金属栅组合多个金属氧化物半导体的多个阈值电压装置公开(公告)号：US20140054717A1
公开(公告)日：2014-02-27
申请号：US13594772
申请日：2012-08-24
IPC分类号： H01L21/283 , H01L27/092
CPC分类号： H01L27/0922 , H01L21/28088 , H01L21/823835 , H01L21/823842 , H01L27/088 , H01L29/45 , H01L29/4966 , H01L29/517
摘要： A substrate is provided, having formed thereon a first region and a second region of a complementary type to the first region. A gate dielectric is deposited over the substrate, and a first full metal gate stack is deposited over the gate dielectric. The first full metal gate stack is removed over the first region to produce a resulting structure. Over the resulting structure, a second full metal gate stack is deposited, in contact with the gate dielectric over the first region. The first and second full metal gate stacks are encapsulated.
摘要翻译： 提供了基板，其上形成有与第一区域互补的第一区域和第二区域。 在衬底上沉积栅极电介质，并且在栅极电介质上沉积第一全金属栅极堆叠。 在第一区域上去除第一个全金属栅极叠层，以产生结果。 在所得到的结构上，在第一区域上沉积与栅极电介质接触的第二全金属栅极堆叠。 第一和第二全金属栅极堆叠被封装。
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47.发明授权公开(公告)号：US08617961B1
公开(公告)日：2013-12-31
申请号：US13551659
申请日：2012-07-18
IPC分类号： H01L21/76
CPC分类号： H01L21/76283 , H01L21/823431 , H01L21/845 , H01L29/66545
摘要： A method for fin field effect transistor (finFET) device formation includes forming a plurality of fins on a substrate; forming a gate region over the plurality of fins; and forming isolation areas for the finFET device after formation of the gate region, wherein forming the isolation areas for the finFET device comprises performing one of oxidation or removal of a subset of the plurality of fins.
摘要翻译： 鳍状场效应晶体管（finFET）器件形成的方法包括在衬底上形成多个翅片; 在所述多个翅片上形成栅极区域; 以及在形成栅极区域之后形成用于finFET器件的隔离区域，其中形成用于finFET器件的隔离区域包括执行多个鳍片的子集的氧化或去除之一。
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48.发明申请公开(公告)号：US20130295730A1
公开(公告)日：2013-11-07
申请号：US13487511
申请日：2012-06-04
申请人： Thomas N. Adam , Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Pranita Kulkarni , Alexander Reznicek
发明人： Thomas N. Adam , Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Pranita Kulkarni , Alexander Reznicek
IPC分类号： H01L21/336
CPC分类号： H01L27/1203 , H01L21/84
摘要： A method of creating a semiconductor integrated circuit is disclosed. The method includes forming a first field effect transistor (FET) device and a second FET device on a semiconductor substrate. The method includes epitaxially growing raised source/drain (RSD) structures for the first FET device at a first height. The method includes epitaxially growing raised source/drain (RSD) structures for the second FET device at a second height. The second height is greater than the first height such that a threshold voltage of the second FET device is greater than a threshold voltage of the first FET device.
摘要翻译： 公开了一种制造半导体集成电路的方法。 该方法包括在半导体衬底上形成第一场效应晶体管（FET）器件和第二FET器件。 该方法包括在第一高度上外延生长用于第一FET器件的升高的源极/漏极（RSD）结构。 该方法包括在第二高度上外延生长用于第二FET器件的升高的源极/漏极（RSD）结构。 第二高度大于第一高度，使得第二FET器件的阈值电压大于第一FET器件的阈值电压。
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公开(公告)号：US20120292705A1
公开(公告)日：2012-11-22
申请号：US13108290
申请日：2011-05-16
申请人： Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L27/092
CPC分类号： H01L27/1203 , H01L21/823864 , H01L21/823892
摘要： A semiconductor structure which includes a semiconductor on insulator (SOI) substrate. The SOI substrate includes a base semiconductor layer; a buried oxide (BOX) layer in contact with the base semiconductor layer; and an SOI layer in contact with the BOX layer. The semiconductor structure further includes a circuit formed with respect to the SOI layer, the circuit including an N type field effect transistor (NFET) having source and drain extensions in the SOI layer and a gate; and a P type field effect transistor (PFET) having source and drain extensions in the SOI layer and a gate. There may also be a well under each of the NFET and PFET. There is a nonzero electrical bias being applied to the. SOI substrate. One of the NFET extensions and PFET extensions may be underlapped with respect to the NFET gate or PFET gate, respectively.
摘要翻译： 一种半导体结构，其包括绝缘体上半导体（SOI）基板。 SOI衬底包括基极半导体层; 与基底半导体层接触的掩埋氧化物（BOX）层; 以及与BOX层接触的SOI层。 半导体结构还包括相对于SOI层形成的电路，该电路包括在SOI层中具有源极和漏极延伸的N型场效应晶体管（NFET）和栅极; 以及在SOI层中具有源极和漏极延伸的P型场效应晶体管（PFET）和栅极。 每个NFET和PFET下面也可以有一个阱。 有一个非零的电偏压被施加到。 SOI衬底。 NFET扩展和PFET扩展中的一个可能分别相对于NFET栅极或PFET栅极被覆盖。
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公开(公告)号：US20120280290A1
公开(公告)日：2012-11-08
申请号：US13102073
申请日：2011-05-06
申请人： Ali Khakifirooz , Kangguo Cheng , Bruce B. Doris , Wilfried E. Haensch , Balasubramanian S. Haran , Pranita Kulkarni
发明人： Ali Khakifirooz , Kangguo Cheng , Bruce B. Doris , Wilfried E. Haensch , Balasubramanian S. Haran , Pranita Kulkarni
IPC分类号： H01L29/772 , H01L21/28
CPC分类号： H01L27/0207 , H01L21/28518 , H01L21/76802 , H01L21/76895 , H01L21/76897 , H01L21/823425 , H01L21/823437 , H01L21/823475 , H01L27/1104 , H01L29/41783 , H01L29/66545 , H01L29/6659 , H01L29/7834
摘要： A common cut mask is employed to define a gate pattern and a local interconnect pattern so that local interconnect structures and gate structures are formed with zero overlay variation relative to one another. A local interconnect structure may be laterally spaced from a gate structure in a first horizontal direction, and contact another gate structure in a second horizontal direction that is different from the first horizontal direction. Further, a gate structure may be formed to be collinear with a local interconnect structure that adjoins the gate structure. The local interconnect structures and the gate structures are formed by a common damascene processing step so that the top surfaces of the gate structures and the local interconnect structures are coplanar with each other.
摘要翻译： 采用公共切割掩模来限定栅极图案和局部互连图案，使得局部互连结构和栅极结构相对于彼此形成为零覆盖变化。 局部互连结构可以在第一水平方向上与栅极结构横向间隔开，并且在与第一水平方向不同的第二水平方向上接触另一个栅极结构。 此外，栅极结构可以形成为与邻接栅极结构的局部互连结构共线。 局部互连结构和栅极结构通过公共镶嵌处理步骤形成，使得栅极结构的顶表面和局部互连结构彼此共面。
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