公开(公告)号：US08138024B2

公开(公告)日：2012-03-20

申请号：US12037774

申请日：2008-02-26

申请人： Byung Tai Do ,  Rui Huang ,  Seng Guan Chow ,  Heap Hoe Kuan

发明人： Byung Tai Do ,  Rui Huang ,  Seng Guan Chow ,  Heap Hoe Kuan

IPC分类号： H01L21/56 ,  H01L23/552

CPC分类号： H01L23/3128 ,  H01L21/56 ,  H01L23/552 ,  H01L24/48 ,  H01L24/73 ,  H01L24/91 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A method of manufacturing a package system includes: providing a semiconductor die with a contact pad and a ground pad, mounting the semiconductor die on a package substrate using and adhesive layer, forming a vertical conductive structure on top of the ground pad in the semiconductor die, encapsulating at least portions of the semiconductor die, the vertical conductive structure, and the package substrate using an encapsulant, covering at least portions of the encapsulant and the vertical conductive structure with a shielding layer to place the vertical conductive structure in electrical contact with the shielding layer, and connecting the shielding layer to the package substrate.

摘要翻译： 制造封装系统的方法包括：提供具有接触焊盘和接地焊盘的半导体管芯，使用粘合剂层将半导体管芯安装在封装衬底上，在半导体管芯中的接地焊盘顶部形成垂直导电结构 ，使用密封剂封装半导体管芯，垂直导电结构和封装衬底的至少一部分，用屏蔽层覆盖至少一部分密封剂和垂直导电结构，以使垂直导电结构与 屏蔽层，并且将屏蔽层连接到封装基板。

公开(公告)号：US08084302B2

公开(公告)日：2011-12-27

申请号：US12044803

申请日：2008-03-07

申请人： Byung Tai Do ,  Seng Guan Chow ,  Heap Hoe Kuan ,  Linda Pei Ee Chua ,  Rui Huang

发明人： Byung Tai Do ,  Seng Guan Chow ,  Heap Hoe Kuan ,  Linda Pei Ee Chua ,  Rui Huang

IPC分类号： H01L23/485

CPC分类号： H01L24/19 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor wafer is made by forming a first conductive layer over a sacrificial substrate, mounting a semiconductor die to the sacrificial substrate, depositing an insulating layer over the semiconductor die and first conductive layer, exposing the first conductive layer and contact pad on the semiconductor die, forming a second conductive layer over the insulating layer between the first conductive layer and contact pad, forming solder bumps on the second conductive layer, depositing an encapsulant over the semiconductor die, first conductive layer, and interconnect structure, and removing the sacrificial substrate after forming the encapsulant to expose the conductive layer and semiconductor die. A portion of the encapsulant is removed to expose a portion of the solder bumps. The solder bumps are sized so that each extends the same outside the encapsulant. The semiconductor die are stacked by electrically connecting the solder bumps.

摘要翻译： 通过在牺牲衬底上形成第一导电层，将半导体管芯安装到牺牲衬底上，在半导体管芯和第一导电层上方沉积绝缘层，暴露半导体管芯上的第一导电层和接触焊盘来制造半导体晶片 在所述第一导电层和所述接触焊盘之间的所述绝缘层上方形成第二导电层，在所述第二导电层上形成焊料凸点，在所述半导体管芯上方沉积密封剂，所述第一导电层和互连结构， 形成密封剂以暴露导电层和半导体管芯。 去除一部分密封剂以露出焊料凸块的一部分。 焊料凸块的尺寸设计成使得每个焊料凸块在封装体外均延伸。 通过电连接焊料凸块来堆叠半导体管芯。

公开(公告)号：US07923846B2

公开(公告)日：2011-04-12

申请号：US12121752

申请日：2008-05-15

申请人： Byung Tai Do ,  Seng Guan Chow ,  Heap Hoe Kuan ,  Linda Pei Ee Chua ,  Rui Huang

发明人： Byung Tai Do ,  Seng Guan Chow ,  Heap Hoe Kuan ,  Linda Pei Ee Chua ,  Rui Huang

IPC分类号： H01L23/48

CPC分类号： H01L23/49548 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/4334 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A multiple encapsulation integrated circuit package-in-package system includes: dicing a top integrated circuit wafer having a bottom encapsulant thereon to form a top integrated circuit die with the bottom encapsulant; positioning internal leadfingers adjacent and connected to a bottom integrated circuit die; pressing the bottom encapsulant on to the bottom integrated circuit die; connecting the top integrated circuit die to external leadfingers adjacent the internal leadfingers; and forming a top encapsulant over the top integrated circuit die.

摘要翻译： 多封装集成电路封装包装系统包括：在其上划分具有底部密封剂的顶部集成电路晶片，以形成具有底部密封剂的顶部集成电路裸片; 将内部引线定位在相邻并连接到底部集成电路管芯上; 将底部密封剂压在底部集成电路模具上; 将顶部集成电路管芯连接到与内部引线管相邻的外部引线管; 以及在顶部集成电路管芯上形成顶部密封剂。

公开(公告)号：US20100270661A1

公开(公告)日：2010-10-28

申请号：US12830390

申请日：2010-07-05

申请人： Reza A. Pagaila ,  Byung Tai Do ,  Yaojian Lin ,  Rui Huang

发明人： Reza A. Pagaila ,  Byung Tai Do ,  Yaojian Lin ,  Rui Huang

IPC分类号： H01L23/52

CPC分类号： H01L23/3128 ,  H01L23/29 ,  H01L23/3121 ,  H01L23/552 ,  H01L24/48 ,  H01L25/165 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device has an IPD structure formed over a substrate. First and second electrical devices are mounted to a first surface of the IPD structure. An encapsulant is deposited over the first and second electrical devices and IPD structure. A shielding layer is formed over the encapsulant and electrically connected to a conductive channel in the IPD structure. The conductive channel is connected to ground potential to isolate the first and second electrical devices from external interference. A recess can be formed in the encapsulant material between the first and second electrical devices. The shielding layer extends into the recess. An interconnect structure is formed on a second surface of the IPD structure. The interconnect structure is electrically connected to the first and second electrical devices and IPD structure. A shielding cage can be formed over the first electrical device prior to depositing encapsulant.

摘要翻译： 半导体器件具有在衬底上形成的IPD结构。 第一和第二电气装置安装在IPD结构的第一表面上。 密封剂沉积在第一和第二电气设备和IPD结构上。 屏蔽层形成在密封剂之上并电连接到IPD结构中的导电通道。 导电通道连接到地电位，以隔离第一和第二电气装置与外部干扰。 可以在第一和第二电气装置之间的密封剂材料中形成凹部。 屏蔽层延伸到凹槽中。 互连结构形成在IPD结构的第二表面上。 互连结构电连接到第一和第二电气设备和IPD结构。 在沉积密封剂之前，可以在第一电气装置上形成屏蔽笼。

公开(公告)号：US20100019359A1

公开(公告)日：2010-01-28

申请号：US12572568

申请日：2009-10-02

申请人： Reza A. Pagaila ,  Byung Tai Do ,  Rui Huang

发明人： Reza A. Pagaila ,  Byung Tai Do ,  Rui Huang

IPC分类号： H01L23/31 ,  H01L23/522

CPC分类号： H01L25/105 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/29 ,  H01L23/3114 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L24/82 ,  H01L24/96 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/12105 ,  H01L2224/48091 ,  H01L2224/48471 ,  H01L2224/73265 ,  H01L2224/85385 ,  H01L2225/06527 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device has a semiconductor die with a peripheral region around the die. A first insulating material is deposited in the peripheral region. A conductive via is formed through the first insulating material. A conductive layer is formed over the semiconductor die. The conductive layer is electrically connected between the conductive via and a contact pad of the semiconductor die. A second insulating layer is deposited over the first insulating layer, conductive layer, and semiconductor die. A profile is formed in the first and second insulating layers in the peripheral region. The profile is tapered, V-shaped, truncated V-shape, flat, or vertical. A shielding layer is formed over the first and second insulating layers to isolate the semiconductor die from inter-device interference. The shielding layer conforms to the profile in the peripheral region and electrically connects the shielding layer to the conductive via.

摘要翻译： 半导体器件具有半导体管芯，其具有围绕管芯的周边区域。 第一绝缘材料沉积在周边区域中。 通过第一绝缘材料形成导电通孔。 在半导体管芯上形成导电层。 导电层电连接在导电通孔和半导体管芯的接触焊盘之间。 在第一绝缘层，导电层和半导体管芯上沉积第二绝缘层。 在周边区域的第一绝缘层和第二绝缘层中形成轮廓。 型材呈锥形，V形，截头V形，扁平或垂直。 在第一绝缘层和第二绝缘层之上形成屏蔽层以将半导体管芯与器件间干扰隔离。 屏蔽层符合外围区域中的轮廓并将屏蔽层电连接到导电通孔。

公开(公告)号：US20090127720A1

公开(公告)日：2009-05-21

申请号：US12203332

申请日：2008-09-03

申请人： Byung Tai Do ,  Heap Hoe Kuan ,  Rui Huang

发明人： Byung Tai Do ,  Heap Hoe Kuan ,  Rui Huang

IPC分类号： H01L23/28 ,  H01L21/56

CPC分类号： H01L23/49548 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/4334 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An integrated circuit package system includes: providing an integrated circuit; mounting a lead on the periphery of the integrated circuit; connecting the integrated circuit to the lead with an interconnect; and forming a conformable material by pressing the conformable material on the integrated circuit, the lead, and the interconnect.

摘要翻译： 集成电路封装系统包括：提供集成电路; 在集成电路的外围安装引线; 通过互连将集成电路连接到引线; 以及通过在集成电路，引线和互连上按压适形材料来形成适形材料。

公开(公告)号：US20090127680A1

公开(公告)日：2009-05-21

申请号：US12121752

申请日：2008-05-15

申请人： Byung Tai Do ,  Seng Guan Chow ,  Heap Hoe Kuan ,  Linda Pei Ee Chua ,  Rui Huang

发明人： Byung Tai Do ,  Seng Guan Chow ,  Heap Hoe Kuan ,  Linda Pei Ee Chua ,  Rui Huang

IPC分类号： H01L23/495 ,  H01L21/00

CPC分类号： H01L23/49548 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/4334 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A multiple encapsulation integrated circuit package-in-package system includes: dicing a top integrated circuit wafer having a bottom encapsulant thereon to form a top integrated circuit die with the bottom encapsulant; positioning internal leadfingers adjacent and connected to a bottom integrated circuit die; pressing the bottom encapsulant on to the bottom integrated circuit die; connecting the top integrated circuit die to external leadfingers adjacent the internal leadfingers; and forming a top encapsulant over the top integrated circuit die.

摘要翻译： 多封装集成电路封装包装系统包括：在其上划分具有底部密封剂的顶部集成电路晶片，以形成具有底部密封剂的顶部集成电路裸片; 将内部引线定位在相邻并连接到底部集成电路管芯上; 将底部密封剂压在底部集成电路模具上; 将顶部集成电路管芯连接到与内部引线管相邻的外部引线管; 以及在顶部集成电路管芯上形成顶部密封剂。

公开(公告)号：US20210329618A1

公开(公告)日：2021-10-21

申请号：US17320942

申请日：2021-05-14

申请人： Andrey Chervyakov ,  Rui Huang ,  Hua Li ,  Yi Guo ,  Qiming Li

发明人： Andrey Chervyakov ,  Rui Huang ,  Hua Li ,  Yi Guo ,  Qiming Li

IPC分类号： H04W72/04 ,  H04W72/12 ,  H04W56/00 ,  H04L5/00

摘要： An apparatus of a New Radio (NR) Node B (gNB), a method, and a storage medium. One or more processors of the apparatus are to: encode for transmission to a user equipment (UE) a message to configure the UE with a measurement gap pattern for positioning reference signal (PRS) measurements; and set a gap pattern length of a measurement gap corresponding to the measurement gap pattern depending on whether an overlap exists between a PRS to be measured and one or more other NR data scheduled to be received by the UE.

公开(公告)号：US20210022105A1

公开(公告)日：2021-01-21

申请号：US17061032

申请日：2020-10-01

申请人： Zhibin Yu ,  Rui Huang ,  Andrey Chervyakov ,  Alexey Khoryaev ,  Qiming Li

发明人： Zhibin Yu ,  Rui Huang ,  Andrey Chervyakov ,  Alexey Khoryaev ,  Qiming Li

IPC分类号： H04W64/00 ,  G01S5/10 ,  G01S1/20

摘要： An apparatus for use in a UE includes processing circuitry coupled to a memory. To configure the UE for Reference Signal Time Difference (RSTD)-based 5G-NR positioning. The processing circuitry is to determine a first PRS BW associated with a first PRS received from a first gNB associated with a first cell. A second PRS BW is determined, which is associated with a second PRS received from a second gNB of a second cell. An RSTD report resolution is determined based on the first PRS BW and the second PRS BW. A receive (Rx) timing difference between the first cell and the second cell is measured based on reception times of the first PRS and the second PRS. The measured Rx timing difference is mapped into an RSTD report for transmission to the first gNB, based on the RSTD report resolution.

公开(公告)号：US09743289B2

公开(公告)日：2017-08-22

申请号：US14583263

申请日：2014-12-26

申请人： Candy Yiu ,  Yang Tang ,  Rui Huang

发明人： Candy Yiu ,  Yang Tang ,  Rui Huang

IPC分类号： H04W24/02 ,  H04W72/10 ,  H04W72/04 ,  H04W72/02

CPC分类号： H04W24/02 ,  H04W36/0083 ,  H04W72/02 ,  H04W72/0426 ,  H04W72/10

摘要： Systems and methods for prioritizing inter-frequency measurement are disclosed herein. User equipment (UE) may be configured to communicatively couple to an Evolved Universal Terrestrial Radio Access Network (E-UTRAN) Node B (eNB). The eNB may determine a priority for performing each of a plurality of inter-frequency measurement. The eNB may indicate the priority of each measurement to the UE. The eNB may transmit lists of higher priority and lower priority measurement objects. The lists may be separate and/or concatenated. Alternatively, or in addition, each measurement object may include a priority indicator, or the priority may be determined from the type of measurement object. In some embodiments, the eNB may provide indications of normal priority and low priority measurement objects and/or indications of normal priority and high priority measurement objects. The UE may perform measurements according to the indicated priorities.