公开(公告)号：US20090065902A1

公开(公告)日：2009-03-12

申请号：US11853428

申请日：2007-09-11

申请人： Cheemen Yu ,  Chih-Chin Liao ,  Hem Takiar

发明人： Cheemen Yu ,  Chih-Chin Liao ,  Hem Takiar

IPC分类号： H01L29/06 ,  H01L21/304 ,  H01L21/56

CPC分类号： H01L21/3043 ,  H01L21/78 ,  H01L23/3121 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05554 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24145 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2224/97 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method of forming a low profile semiconductor package, and a semiconductor package formed thereby, is disclosed. The semiconductor die is formed with one or more sloped edges on which electrically conductive traces may be deposited to allow the semiconductor die to be coupled to another die and/or a substrate on which the die is mounted. Depositing the electrical traces directly on the surface and sloped edge of the die allows the die to be electrically coupled without bond wires, thereby allowing a reduction in the overall thickness of the package.

摘要翻译： 公开了一种形成低轮廓半导体封装的方法，以及由此形成的半导体封装。 半导体管芯形成有一个或多个倾斜边缘，导电迹线可以沉积在其上，以允许半导体管芯耦合到另一管芯和/或其上安装管芯的衬底。 将电迹线直接沉积在模具的表面和倾斜边缘上，使得模具能够电耦合而没有接合线，从而允许减小包装的整体厚度。

公开(公告)号：US20070210444A1

公开(公告)日：2007-09-13

申请号：US11373941

申请日：2006-03-13

申请人： Che-Jung Chang ,  Chin-Tien Chiu ,  Cheemen Yu ,  Hem Takiar ,  Jack Chien ,  Ning Liu

发明人： Che-Jung Chang ,  Chin-Tien Chiu ,  Cheemen Yu ,  Hem Takiar ,  Jack Chien ,  Ning Liu

IPC分类号： H01L23/12

CPC分类号： G06K19/077 ,  B29C45/14311 ,  B29C45/14647 ,  B29C2045/14327 ,  G06K19/07724 ,  G06K19/07732 ,  H01L23/10 ,  H01L23/544 ,  H01L24/48 ,  H01L24/97 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A flash memory card and methods of manufacturing same are disclosed. The card includes a semiconductor package fabricated to receive a single-sided or double-sided lid. A surface of the semiconductor package may be formed with holes, trenches and/or pockmarks. After the holes, trenches and/or pockmarks are formed, a lid may be attached to the package surface in an injection molding process. During the injection molding process, the molten plastic flows into the holes, trenches and/or pockmarks to interconnect with the surface of the semiconductor package. Thus, when the molten plastic hardens, the holes, trenches and/or pockmarks ensure that the lid remains firmly attached to semiconductor package.

摘要翻译： 公开了一种闪存卡及其制造方法。 卡包括制造成接收单面或双面盖的半导体封装。 半导体封装的表面可以形成有孔，沟槽和/或戳记。 在形成孔，沟和/或标记之后，可以在注射成型工艺中将盖子附接到包装表面。 在注射成型过程中，熔融的塑料流入与半导体封装的表面互连的孔，沟槽和/或戳痕。 因此，当熔融塑料硬化时，孔，沟槽和/或戳痕确保盖保持牢固地附接到半导体封装。

公开(公告)号：US07772107B2

公开(公告)日：2010-08-10

申请号：US11538220

申请日：2006-10-03

申请人： Cheemen Yu ,  Hem Takiar ,  Chih-Chin Liao

发明人： Cheemen Yu ,  Hem Takiar ,  Chih-Chin Liao

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L21/4846 ,  H01L21/486 ,  H01L23/49827 ,  H01L2224/48091 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/00014

摘要： Methods of forming a semiconductor package including a single-sided substrate are disclosed. In a first embodiment of the present invention, a substrate may include a conductive layer on a top surface of the substrate, i.e., on the same side of the substrate as where the die are mounted. In a second embodiment of the present invention, a substrate may include a conductive layer on a bottom of the substrate, i.e., on the opposite side of the substrate as where the die are mounted.

摘要翻译： 公开了形成包括单面基板的半导体封装的方法。 在本发明的第一实施例中，衬底可以在衬底的顶表面上，即在衬底的与安装裸片相同的一侧上包括导电层。 在本发明的第二实施例中，衬底可以包括在衬底的底部上的导电层，即衬底的安装模具的相反侧。

公开(公告)号：US20070096285A1

公开(公告)日：2007-05-03

申请号：US11265336

申请日：2005-11-02

申请人： Chin-Tien Chiu ,  Jack Chien ,  Meng-Ju Tsai ,  Cheemen Yu ,  Hem Takiar

发明人： Chin-Tien Chiu ,  Jack Chien ,  Meng-Ju Tsai ,  Cheemen Yu ,  Hem Takiar

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  H01L23/3121 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/2919 ,  H01L2224/32057 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83385 ,  H01L2224/8385 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/078 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor die substrate is disclosed for preventing delamination of the die and/or die cracking due to air bubbles trapped beneath the die, and a semiconductor package incorporating the substrate. A solder mask may be laminated on a surface of the substrate which is patterned with one or more passageways, or canals, allowing air bubbles to be expelled from beneath the semiconductor die during the semiconductor package fabrication. The canals may have a variety of shapes, including for example a wavy, undulating shape.

摘要翻译： 公开了一种半导体管芯基板，用于防止由于在管芯下面捕获的气泡引起的管芯剥离和/或模头裂纹，以及结合该衬底的半导体封装。 焊接掩模可以层压在衬底的表面上，其被图案化为具有一个或多个通道或通道，允许在半导体封装制造期间将气泡从半导体管芯下方排出。 运河可以具有各种形状，包括例如波浪形起伏的形状。

公开(公告)号：US20070262434A1

公开(公告)日：2007-11-15

申请号：US11782102

申请日：2007-07-24

申请人： Chin-Tien Chiu ,  Cheemen Yu ,  Hem Takiar ,  Jack Chien ,  Meng-Ju Tsai

发明人： Chin-Tien Chiu ,  Cheemen Yu ,  Hem Takiar ,  Jack Chien ,  Meng-Ju Tsai

IPC分类号： H01L23/02

CPC分类号： H01L23/49805 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06562 ,  H01L2225/1005 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H05K1/142 ,  H05K3/0052 ,  H05K3/3442 ,  H05K3/403 ,  H05K2201/09963 ,  H05K2201/1053 ,  H05K2201/10727 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An electronic component is disclosed including a plurality of semiconductor packages soldered together in a side-by-side configuration. The packages are batch processed on a substrate panel. The panel includes a plurality of through-holes drilled through the panel and subsequently filled with metal such as copper or gold. These filled through-holes lie along the cut line between adjacent packages so that, upon singulation, the filled through holes are cut and a portion of the filled through-holes are exposed at the side edges of the singulated packages. These exposed portions of the filled through-holes form vertical surface mount technology (SMT) pads. After the semiconductor packages are singulated and the SMT pads are defined in the side edges, SMT is used to solder the SMT pads of a first semiconductor package to the respective SMT pads of a second semiconductor package to structurally and electrically couple the two packages together side-by-side.

摘要翻译： 公开了一种电子部件，其包括以并排配置焊接在一起的多个半导体封装。 包装在基板上进行批量处理。 面板包括穿过面板钻出的多个通孔，随后填充有诸如铜或金的金属。 这些填充的通孔沿着相邻封装之间的切割线位于相邻封装之间的切割线处，使得在分离时，填充的通孔被切割并且一部分填充的通孔在单个封装的侧边缘处露出。 填充的通孔的这些暴露部分形成垂直表面贴装技术（SMT）焊盘。 在半导体封装被单个化并且SMT焊盘限定在侧边缘中之后，使用SMT来将第一半导体封装的SMT焊盘焊接到第二半导体封装的相应SMT焊盘，以将两个封装结合和电耦合在一起 旁边。

公开(公告)号：US08470640B2

公开(公告)日：2013-06-25

申请号：US12165297

申请日：2008-06-30

申请人： Hem Takiar ,  Shrikar Bhagath ,  Cheemen Yu ,  Chih-Chin Liao

发明人： Hem Takiar ,  Shrikar Bhagath ,  Cheemen Yu ,  Chih-Chin Liao

IPC分类号： H01L21/00

CPC分类号： H01L24/85 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05553 ,  H01L2224/32506 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49174 ,  H01L2224/83801 ,  H01L2224/85 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/04953 ,  H01L2924/078 ,  H01L2924/10155 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2224/78 ,  H01L2924/3512 ,  H01L2924/00

摘要： A method of fabricating a semiconductor die and a low profile semiconductor package are disclosed. The semiconductor package may include at least first and second stacked semiconductor die mounted to a substrate. The first and/or second semiconductor die may be fabricated with localized cavities through a bottom surface of the semiconductor die, along a side edge of the semiconductor die. The one or more localized cavities in a side take up less than the entire side. Thus, the localized cavities allow low height stacking of semiconductor die while providing each die with a high degree of structural integrity to prevent cracking or breaking of the die edge during fabrication.

摘要翻译： 公开了半导体管芯和低剖面半导体封装的制造方法。 半导体封装可以包括安装到衬底的至少第一和第二堆叠半导体管芯。 第一和/或第二半导体管芯可以沿着半导体管芯的侧边缘通过半导体管芯的底表面被制造成具有局部空腔。 一个侧面中的一个或多个局部空腔占据整个侧面。 因此，局部空腔允许半导体芯片的低高度堆叠，同时为每个模具提供高度的结构完整性，以防止在制造期间模头边缘的破裂或断裂。

公开(公告)号：US20100102440A1

公开(公告)日：2010-04-29

申请号：US12648697

申请日：2009-12-29

申请人： Cheemen Yu ,  Chih-Chin Liao ,  Hem Takiar

发明人： Cheemen Yu ,  Chih-Chin Liao ,  Hem Takiar

IPC分类号： H01L25/16 ,  H01L23/04

CPC分类号： H01L25/0657 ,  G11C5/02 ,  G11C5/04 ,  G11C5/143 ,  G11C8/12 ,  H01L21/485 ,  H01L23/5382 ,  H01L25/50 ,  H01L2225/06527 ,  H01L2225/06579 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor package is disclosed including a plurality semiconductor die mounted on stacked and bonded layers of substrate, for example polyimide tape used in tape automated bonding processes. The tape may have a plurality of repeating patterns of traces and contact pads formed thereon. The traces each include aligned interconnect pads on the respective top and bottom surfaces of the substrate for bonding the traces of one pattern to the traces of another pattern after the patterns have been singulated from the substrate, aligned and stacked. Semiconductor die such as flash memory and a controller die are mounted on the traces of the respective patterns on the substrate. In order for the controller die to uniquely address a specific flash memory die in the stack, a group of traces on each substrate supporting the memory die are used as address pins and punched in a unique layout relative to the layout of the traces other substrates. By providing each flash memory semiconductor die on a substrate with a unique layout of address traces, each memory die may be selectively addressed by the controller die.

摘要翻译： 公开了一种半导体封装，其包括安装在基板的堆叠和接合层上的多个半导体管芯，例如在带自动焊接工艺中使用的聚酰亚胺带。 带可以具有多个重复图案的迹线和形成在其上的接触垫。 每个迹线包括在衬底的相应顶部和底部表面上的对准的互连焊盘，用于在将图案从基板切割成对准和堆叠之后将一个图案的迹线粘合到另一图案的迹线。 诸如闪速存储器和控制器管芯的半导体管芯安装在衬底上各个图案的迹线上。 为了使控制器裸片独特地寻址堆叠中的特定闪存芯片，支持存储芯片的每个衬底上的一组迹线被用作地址引脚，并相对于其它衬底的迹线的布局以独特的布局冲压。 通过在基板上提供具有唯一的地址迹线布局的每个闪速存储器半导体管芯，每个存储管芯可以被控制器管芯选择性地寻址。

公开(公告)号：US20080182365A1

公开(公告)日：2008-07-31

申请号：US12060418

申请日：2008-04-01

申请人： Ming Hsun Lee ,  Chih-Chin Liao ,  Cheemen Yu ,  Hem Takiar

发明人： Ming Hsun Lee ,  Chih-Chin Liao ,  Cheemen Yu ,  Hem Takiar

IPC分类号： H01L21/60

CPC分类号： H01L23/4951 ,  H01L23/49551 ,  H01L23/49558 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05553 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A leadframe for a semiconductor package is disclosed including electrical leads which extend from one side of the leadframe to an opposite side of the leadframe, where electrical connection may be made with the semiconductor die at the second side of the leadframe. The semiconductor die may be supported on the leads extending across the leadframe. The package may further include a spacer layer affixed to the electrical leads to fortify the semiconductor package and to prevent exposure of the electrical leads during the molding of the package.

摘要翻译： 公开了一种用于半导体封装的引线框架，其包括从引线框架的一侧延伸到引线框架的相反侧的电引线，其中可以在引线框架的第二侧与半导体管芯进行电连接。 半导体管芯可以被支撑在引导框架上延伸的引线上。 封装还可以包括固定到电引线上的间隔层，以强化半导体封装并防止在封装成型期间电引线的暴露。

公开(公告)号：US20080001303A1

公开(公告)日：2008-01-03

申请号：US11427689

申请日：2006-06-29

申请人： Cheemen Yu ,  Chih-Chin Liao ,  Hem Takiar

发明人： Cheemen Yu ,  Chih-Chin Liao ,  Hem Takiar

IPC分类号： H01L23/52

CPC分类号： H01L25/0657 ,  H01L23/3121 ,  H01L24/73 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： An electronic component is disclosed including a plurality of stacked semiconductor packages. A first such embodiment includes an internal connector for electrically coupling the stacked semiconductor packages. A second such embodiment includes an external connector for electrically coupling the stacked semiconductor packages.

摘要翻译： 公开了一种包括多个堆叠的半导体封装的电子部件。 第一个这样的实施例包括用于电耦合堆叠的半导体封装的内部连接器。 第二个这样的实施例包括用于电耦合堆叠的半导体封装的外部连接器。

公开(公告)号：US20070235848A1

公开(公告)日：2007-10-11

申请号：US11392236

申请日：2006-03-29

申请人： Chih-Chin Liao ,  Cheemen Yu ,  Hem Takiar

发明人： Chih-Chin Liao ,  Cheemen Yu ,  Hem Takiar

IPC分类号： H01L23/48 ,  H01L21/00

CPC分类号： H01L21/4846 ,  H01L2224/48091 ,  H01L2224/48227 ,  H05K1/117 ,  H05K3/242 ,  H05K2203/107 ,  H05K2203/162 ,  H05K2203/175 ,  H01L2924/00014

摘要： A semiconductor die substrate panel, and method of forming same, are disclosed wherein plating bars are severed for example by a laser after electroplating of the substrate. Severing the plating bars allows electrical testing of the substrate prior to attachment of electronic components.

摘要翻译： 公开了一种半导体管芯衬底面板及其形成方法，其中电镀棒例如在电镀电镀之后被激光切断。 切割电镀棒允许在电子部件附着之前对基板进行电气测试。