公开(公告)号：US09286218B2

公开(公告)日：2016-03-15

申请号：US14495151

申请日：2014-09-24

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam

IPC: G11C7/12 ,  G11C11/16 ,  G11C7/08 ,  G06F12/08 ,  G11C11/4094 ,  G11C11/419 ,  G11C11/4091 ,  G11C11/56

CPC classification number: G11C11/1675 ,  G06F12/0806 ,  G06F12/0879 ,  G06F2212/62 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/12 ,  G11C7/22 ,  G11C11/16 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/419 ,  G11C11/5607 ,  Y02D10/13

Abstract: In a spin-torque magnetic random access memory (MRAM) that includes local source lines, auto-booting of the word line is used to conserve power consumption by reusing charge already present from driving a plurality of bit lines during writing operations. Auto-booting is accomplished by first driving the word line to a first word line voltage. After such driving, the word line isolated. Subsequent driving of the plurality of bit lines that are capacitively coupled to the word line causes the word line voltage to be increased to a level desired to allow sufficient current to flow through a selected memory cell to write information into the selected memory cell. Additional embodiments include the use of a supplemental voltage provider that is able to further boost or hold the isolated word line at the needed voltage level.

Abstract translation: 在包括本地源线的自旋扭矩磁随机存取存储器（MRAM）中，字线的自动引导用于通过在写入操作期间重新使用已经存在的驱动多个位线的电荷来节省功耗。 通过首先将字线驱动到第一字线电压来实现自动启动。 经过这样的驾驶，字线隔离。 随后驱动电容耦合到字线的多个位线使得字线电压增加到期望的水平，以允许足够的电流流过选定的存储器单元以将信息写入所选存储单元。 另外的实施例包括使用能够进一步升高或保持隔离字线处于所需电压电平的补充电压提供器。

公开(公告)号：US20160070935A1

公开(公告)日：2016-03-10

申请号：US14942665

申请日：2015-11-16

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas Andre

IPC: G06F21/79 ,  G06F3/06

CPC classification number: G06F21/79 ,  G06F3/062 ,  G06F3/0653 ,  G06F3/0679 ,  G06F21/78 ,  G06F21/86 ,  G06F2221/2143 ,  G11C7/24 ,  G11C11/1695

Abstract: In response to a tamper-attempt indication, a memory device selectively disables one or more memory operations. Disabling can be accomplished by different techniques, including altering bias voltages associated with performing the memory operation, gating off a current needed for performing the memory operation, and limiting the needed current to a magnitude below the threshold magnitude required for the operation. After disabling the memory operation, a mock current can be generated. The mock current is intended to mimic the current normally expended during the memory operation when not disabled, thereby leading a user to believe that the device is continuing to operate normally even though the memory operation that is being attempted is not actually being performed.

Abstract translation: 响应于篡改尝试指示，存储器设备选择性地禁用一个或多个存储器操作。 禁用可以通过不同的技术实现，包括改变与执行存储器操作相关联的偏置电压，选通执行存储器操作所需的电流，以及将所需电流限制在低于操作所需阈值幅度的幅度。 禁用内存操作后，可以生成模拟电流。 模拟电流旨在模拟在不被禁用时在存储器操作期间通常消耗的电流，从而导致用户认为即使正在尝试的存储器操作实际上不被执行，设备也继续正常地操作。

公开(公告)号：US09245611B2

公开(公告)日：2016-01-26

申请号：US14702828

申请日：2015-05-04

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas Andre ,  Matthew R. Croft ,  Chitra Subramanian ,  Halbert Lin

IPC: G11C11/00 ,  G11C11/16 ,  G06F11/10 ,  G11C29/04 ,  G11C13/00

CPC classification number: G11C11/1675 ,  G06F11/1048 ,  G06F11/1076 ,  G11C11/00 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1693 ,  G11C2013/0076 ,  G11C2029/0411

Abstract: A method includes sampling magnetic bits, applying a write current pulse to the magnetic bits to set them to a first logic state, resampling the magnetic bits, and comparing the results of sampling and resampling to determine the bit state for each magnetic bit. A read or write operation may be received after initiation of writing back magnetic bits having the second state, where the write-back can be aborted for a portion of the bits in the case of a write operation. The write-back may be performed such that different portions of the magnetic bits are written back at different times, thereby staggering the write-back current pulses in time. An offset current may also be used during resampling.

Abstract translation: 一种方法包括采样磁头，将写入电流脉冲施加到磁性位以将其设置为第一逻辑状态，重新采样磁头，以及比较采样和重采样的结果，以确定每个磁性位的位状态。 在开始写入具有第二状态的磁性位之后可以接收读取或写入操作，其中在写入操作的情况下可以针对位的一部分中止回写。 可以执行回写，使得磁头的不同部分在不同的时间被写回，从而及时地交错回写电流脉冲。 在重采样期间也可以使用偏移电流。

公开(公告)号：US20160019139A1

公开(公告)日：2016-01-21

申请号：US14827628

申请日：2015-08-17

Applicant: Everspin Technologies, Inc

Inventor： Syed M. Alam ,  Thomas Andre ,  Dietmar Gogl

IPC: G06F12/02 ,  G11C11/16 ,  G06F12/06 ,  G11C11/4096 ,  G11C7/10 ,  G11C14/00 ,  G11C11/4094

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0685 ,  G06F12/0246 ,  G06F12/0638 ,  G06F13/1694 ,  G06F2212/205 ,  G06F2212/7201 ,  G11C7/1042 ,  G11C7/1072 ,  G11C8/04 ,  G11C11/005 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C14/0036

Abstract: A memory system and memory controller for interleaving volatile and non-volatile memory accesses are described. In the memory system, the memory controller is coupled to the volatile and non-volatile memories using a shared address bus. Activate latencies for the volatile and non-volatile memories are different, and registers are included on the memory controller for storing latency values. Additional registers on the memory controller store precharge latencies for the memories as well as page size for the non-volatile memory. A memory access sequencer on the memory controller asserts appropriate chip select signals to the memories to initiate operations therein.

公开(公告)号：US09135970B2

公开(公告)日：2015-09-15

申请号：US14175337

申请日：2014-02-07

Applicant: Everspin Technologies, Inc.

Inventor： Chitra K. Subramanian ,  Halbert S. Lin ,  Syed M. Alam ,  Thomas Andre

IPC: G11C11/00 ,  G11C5/14 ,  G11C7/24 ,  G11C13/00 ,  G11C11/16

CPC classification number: G06F21/79 ,  G06F21/60 ,  G11C7/14 ,  G11C7/24 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1695 ,  G11C13/0002 ,  G11C13/004 ,  G11C13/0059 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0073

Abstract: A technique for detecting tampering attempts directed at a memory device includes setting each of a plurality of detection memory cells to an initial predetermined state, where corresponding portions of the plurality of detection memory cells are included in each of the arrays of data storage memory cells on the memory device. A plurality of corresponding reference bits on the memory device permanently store information representative of the initial predetermined state of each of the detection memory elements. When a tamper detection check is performed, a comparison between the reference bits and the current state of the detection memory cells is used to determine whether any of the detection memory cells have changed state from their initial predetermined states. Based on the comparison, a tamper detect indication is flagged if a threshold level of change is determined. Once a tampering attempt is detected, responses on the memory device include disabling one or more memory operations and generating a mock current to emulate current expected during normal operation.

Abstract translation: 用于检测针对存储器件的篡改尝试的技术包括将多个检测存储器单元中的每一个设置为初始预定状态，其中多个检测存储器单元的相应部分被包括在每个数据存储单元阵列中 存储设备。 存储器装置上的多个对应的参考位永久地存储表示每个检测存储器元件的初始预定状态的信息。 当执行篡改检测检查时，使用检测存储单元的参考位与当前状态之间的比较来确定检测存储单元中的任何一个是否已经从其初始预定状态改变状态。 基于该比较，如果确定了阈值变化水平，则标记篡改检测指示。 一旦检测到篡改尝试，存储器设备上的响应包括禁用一个或多个存储器操作并产生模拟电流以仿真在正常操作期间预期的电流。

公开(公告)号：US20150243337A1

公开(公告)日：2015-08-27

申请号：US14702828

申请日：2015-05-04

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas Andre ,  Matthew R. Croft ,  Chitra Subramanian ,  Halbert Lin

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G06F11/1048 ,  G06F11/1076 ,  G11C11/00 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1693 ,  G11C2013/0076 ,  G11C2029/0411

Abstract: A method includes sampling magnetic bits, applying a write current pulse to the magnetic bits to set them to a first logic state, resampling the magnetic bits, and comparing the results of sampling and resampling to determine the bit state for each magnetic bit. A read or write operation may be received after initiation of writing back magnetic bits having the second state, where the write-back can be aborted for a portion of the bits in the case of a write operation. The write-back may be performed such that different portions of the magnetic bits are written back at different times, thereby staggering the write-back current pulses in time. An offset current may also be used during resampling.

Abstract translation: 一种方法包括采样磁头，将写入电流脉冲施加到磁性位以将其设置为第一逻辑状态，重新采样磁头，以及比较采样和重采样的结果，以确定每个磁性位的位状态。 在开始写入具有第二状态的磁性位之后可以接收读取或写入操作，其中在写入操作的情况下可以针对位的一部分中止回写。 可以执行回写，使得磁头的不同部分在不同的时间被写回，从而及时地交错回写电流脉冲。 在重采样期间也可以使用偏移电流。

公开(公告)号：US20150029786A1

公开(公告)日：2015-01-29

申请号：US14494180

申请日：2014-09-23

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam ,  Chitra Subramanian

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C7/02 ,  G11C7/065 ,  G11C11/16 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693 ,  G11C2013/0057 ,  G11C2207/002

Abstract: Circuitry and a method provide a plurality of timed control and bias voltages to sense amplifiers and write drivers of a spin-torque magnetoresistive random access memory array for improved power supply noise rejection, increased sensing speed with immunity for bank-to-bank noise coupling, and reduced leakage from off word line select devices in an active column.

Abstract translation: 电路和方法提供多个定时控制和偏置电压来读取自旋转矩磁阻随机存取存储器阵列的放大器和写入驱动器，以改善电源噪声抑制，增加用于存储体到存储体噪声耦合的抗扰度的感测速度， 并减少活动列中的字线选择器件的泄漏。

公开(公告)号：US20130308374A1

公开(公告)日：2013-11-21

申请号：US13892107

申请日：2013-05-10

Applicant: EverSpin Technologies, Inc.

Inventor： Dietmar Gogl ,  Syed M. Alam ,  Thomas Andre

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C5/147 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1697 ,  G11C13/0069 ,  G11C2213/79

Abstract: A cell bias control circuit maximizes the performance of devices in the read/write path of memory cells (magnetic tunnel junction device+transistor) without exceeding leakage current or reliability limits by automatically adjusting multiple control inputs of the read/write path at the memory array according to predefined profiles over supply voltage, temperature, and process corner variations by applying any specific reference parameter profiles to the memory array.

Abstract translation: 电池偏置控制电路通过自动调节存储器阵列上的读/写路径的多个控制输入，使存储器单元（磁隧道结器件+晶体管）的读/写路径中的器件的性能最大化，而不会超过泄漏电流或可靠性限制 根据电源电压，温度和过程角变化的预定义配置，通过将任何特定参考参数配置文件应用于存储器阵列。

公开(公告)号：US20130155763A1

公开(公告)日：2013-06-20

申请号：US13720183

申请日：2012-12-19

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas Andre

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/16 ,  G11C11/165 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1693

Abstract: Circuitry and a method for regulating voltages applied to source and bit lines of a spin-torque magnetoresistive random access memory (ST-MRAM) reduces time-dependent dielectric breakdown stress of the word line transistors. During a read or write operation, only the selected bit lines and source lines are pulled down to a low voltage and/or pulled up to a high voltage depending on the operation (write 0, write 1, and read) being performed. The unselected bit lines and source lines are held at the voltage while separately timed signals pull up or pull down the selected bit lines and source lines during read and write operations.

Abstract translation: 用于调节施加到自旋扭矩磁阻随机存取存储器（ST-MRAM）的源极和位线的电压的电路和方法降低了字线晶体管的时间依赖介电击穿应力。 在读或写操作期间，根据所执行的操作（写0，写1和读），只将所选择的位线和源极线拉低至低电压和/或上拉至高电压。 未选择的位线和源极线保持在电压，而在读取和写入操作期间单独定时的信号上拉或下拉所选位线和源极线。

公开(公告)号：US12167702B2

公开(公告)日：2024-12-10

申请号：US18123729

申请日：2023-03-20

Applicant: Everspin Technologies, Inc.

Inventor： Sumio Ikegawa ,  Han Kyu Lee ,  Sanjeev Aggarwal ,  Jijun Sun ,  Syed M. Alam ,  Thomas Andre

IPC: H10N52/80 ,  H10B61/00 ,  H10N50/85 ,  H10N52/00 ,  H10N52/01

Abstract: The present disclosure is drawn to, among other things, a magnetoresistive device and a magnetoresistive memory comprising a plurality of such magnetoresistive devices. In some aspects, a magnetoresistive device may include a magnetically fixed region, a magnetically free region above or below the magnetically fixed region, and an intermediate region positioned between the magnetically fixed region and the magnetically free region, wherein the intermediate region includes a first dielectric material. The magnetoresistive device may also include encapsulation layers formed on opposing side walls of the magnetically free region, wherein the encapsulation layers include the first dielectric material.