公开(公告)号：US06791083B2

公开(公告)日：2004-09-14

申请号：US10207551

申请日：2002-07-29

申请人： Kevin Chan Ee Peng ,  Yelehanka Ramachandramurthy Pradeep ,  Chua Thow Phock

发明人： Kevin Chan Ee Peng ,  Yelehanka Ramachandramurthy Pradeep ,  Chua Thow Phock

IPC分类号： G01N2300

CPC分类号： H01J37/09 ,  H01J2237/28

摘要： An apparatus for preventing distortion to critical dimension line images formed by a SEM under the influence of external electro-magnetic emissions generating by neighboring manufacturing equipment. The external emission causes a high three sigma A/C component. The correcting apparatus includes an external shielding coil mounted to the column housing of the SEM. A control electro-emission driver is mounted to the external shielding coil in which a variable voltage divider having a transformer with a variable resistor. The variable resistor is adjusted varying the amplitude of the sine wave of the A/C signal thus controlling the electro-emission driver while reducing the effects of the three sigma A/C component.

摘要翻译： 一种用于在由相邻制造设备产生的外部电磁发射的影响下由SEM形成的临界尺寸线图像的变形的装置。 外部发射导致高三西格玛A / C分量。 校正装置包括安装在扫描电镜的柱壳体上的外部屏蔽线圈。 控制发光驱动器安装到外部屏蔽线圈，其中具有变压器的可变分压器具有可变电阻器。 调节可变电阻器改变A / C信号的正弦波的振幅，从而控制电发射驱动器，同时减少三西格玛A / C分量的影响。

公开(公告)号：US06346468B1

公开(公告)日：2002-02-12

申请号：US09502037

申请日：2000-02-11

申请人： Yelehanka Ramachandramurthy Pradeep ,  Subhash Gupta ,  Vijai Komar Chhagan

发明人： Yelehanka Ramachandramurthy Pradeep ,  Subhash Gupta ,  Vijai Komar Chhagan

IPC分类号： H01L213205

CPC分类号： H01L29/6653 ,  H01L21/32137 ,  H01L29/6659

摘要： A method for forming an L-shaped spacer using disposable polysilicon top spacers. A semiconductor structure is provided having a gate structure thereon. A liner oxide layer is formed on the gate structure. A dielectric spacer layer is formed on the liner oxide layer. A disposable polysilicon top spacer layer is formed on the dielectric spacer layer. The disposable polysilicon top spacer layer is anisotropically etched to form disposable polysilicon top spacers. The dielectric spacer layer is etched to form L-shaped dielectric spacers, using the disposable polysilicon top spacers as an etch mask. The disposable polysilicon top spacers are removed leaving an L-shaped dielectric spacer. In one embodiment, lightly doped source and drain regions are formed prior to forming the liner oxide layer and the L-shaped spacers.

摘要翻译： 一种使用一次性多晶硅顶部间隔物形成L形间隔件的方法。 提供其上具有栅极结构的半导体结构。 在栅极结构上形成衬里氧化物层。 介电间隔层形成在衬垫氧化物层上。 一次性多晶硅顶部间隔层形成在电介质间隔层上。 一次性多晶硅顶部间隔层被各向异性蚀刻以形成一次性多晶硅顶部间隔物。 使用一次性多晶硅顶部间隔物作为蚀刻掩模，蚀刻电介质间隔层以形成L形电介质间隔物。 去除一次性多晶硅顶部间隔物，留下L形介电间隔物。 在一个实施例中，在形成衬垫氧化物层和L形间隔物之前形成轻掺杂的源极和漏极区。

公开(公告)号：US06312999B1

公开(公告)日：2001-11-06

申请号：US09819378

申请日：2001-03-29

申请人： Subrahamanyam Chivukula ,  Yelehanka Ramachandramurthy Pradeep ,  Madhusudan Mukhopdhyay ,  Palanivel Balasubramaniam

发明人： Subrahamanyam Chivukula ,  Yelehanka Ramachandramurthy Pradeep ,  Madhusudan Mukhopdhyay ,  Palanivel Balasubramaniam

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L29/665 ,  H01L29/7833

摘要： A method for forming a MOSFET having an LDD structure with minimal lateral dopant diffusion is described. A gate electrode is provided overlying a gate dielectric layer on a semiconductor substrate. Dielectric spacers are formed on sidewalls of the gate electrode. Source and drain regions are formed associated with the gate electrode. The gate electrode and source and drain regions are silicided. Thereafter, the spacers are removed to expose the semiconductor substrate. LDD regions are formed using plasma doping in the exposed semiconductor substrate between the source and drain regions and the gate electrode to complete formation of an LDD structure in the fabrication of an integrated circuit device.

摘要翻译： 描述了一种用于形成具有最小横向掺杂剂扩散的LDD结构的MOSFET的方法。 栅电极被设置在半导体衬底上的栅介电层上。 电介质隔板形成在栅电极的侧壁上。 源极和漏极区域形成为与栅电极相关联。 栅电极和源极和漏极区域被硅化。 此后，去除间隔物以露出半导体衬底。 在源极和漏极区域和栅电极之间的暴露的半导体衬底中使用等离子体掺杂形成LDD区域，以在集成电路器件的制造中完成LDD结构的形成。

公开(公告)号：US06303447B1

公开(公告)日：2001-10-16

申请号：US09502036

申请日：2000-02-11

申请人： Vijai Komar Chhagan ,  Yelehanka Ramachandramurthy Pradeep ,  Mei Sheng Zhou ,  Henry Gerung ,  Simon Chooi

发明人： Vijai Komar Chhagan ,  Yelehanka Ramachandramurthy Pradeep ,  Mei Sheng Zhou ,  Henry Gerung ,  Simon Chooi

IPC分类号： H01L21336

CPC分类号： H01L29/66545 ,  H01L21/28044 ,  H01L21/28114 ,  H01L29/41 ,  H01L29/42376 ,  H01L29/4941

摘要： A method for forming an extended metal gate without poly wrap around effects. A semiconductor structure is provided having a gate structure thereon. The gate structure comprising a gate dielectric layer, a gate silicon layer, a doped silicon oxide layer, and a disposable gate layer stacked sequentially. Spacers are formed on the sidewalls of the gate structure. A dielectric gapfill layer is formed over the semiconductor structure and the gate structure and planarized, stopping on the disposable gate layer. A first silicon nitride layer is formed over the disposable gate layer, and a dielectric layer is formed over the first silicon nitride layer. The dielectric layer is patterned to form a trench over the gate structure; wherein the trench has a width greater than the width of the gate structure. The first silicon nitride layer in the bottom of the trench and the disposable gate layer are removed using one or more selective etching processes. The doped silicon oxide layer is removed using an etch with a high selectivity of doped silicon oxide to undoped silicon oxide. A barrier layer is formed over the gate silicon layer, and a metal gate layer is formed on the barrier layer; whereby the metal gate layer has a greater width than the gate structure.

摘要翻译： 一种用于形成不具有聚环绕效应的延伸金属栅极的方法。 提供其上具有栅极结构的半导体结构。 栅极结构包括依次堆叠的栅极介电层，栅极硅层，掺杂氧化硅层和一次性栅极层。 隔板形成在栅极结构的侧壁上。 在半导体结构和栅极结构之上形成电介质间隙填充层，并在一次性栅极层上停止平坦化。 在一次性栅极层上形成第一氮化硅层，并且在第一氮化硅层上形成电介质层。 图案化电介质层以在栅极结构上形成沟槽; 其中所述沟槽的宽度大于所述栅极结构的宽度。 使用一个或多个选择性蚀刻工艺去除沟槽底部中的第一氮化硅层和一次性栅极层。 使用掺杂的氧化硅对未掺杂的氧化硅具有高选择性的蚀刻来去除掺杂的氧化硅层。 在栅极硅层上形成阻挡层，在阻挡层上形成金属栅极层; 由此金属栅极层具有比栅极结构更大的宽度。

公开(公告)号：US06284613B1

公开(公告)日：2001-09-04

申请号：US09434920

申请日：1999-11-05

申请人： Chivukula Subrahmanyam ,  Yelehanka Ramachandramurthy Pradeep ,  Ramakrishnan Rajagopal

发明人： Chivukula Subrahmanyam ,  Yelehanka Ramachandramurthy Pradeep ,  Ramakrishnan Rajagopal

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/7833 ,  H01L29/7836

摘要： A method for a T-gate and salicide process that allows narrow bottom gate widths below 0.25 &mgr;m and wide top gate widths to allow silicide gate contacts on the top of the T-gate. A dummy gate composed of an insulating material is formed over the substrate. Then we form LDD regions adjacent to the dummy gate preferably by ion implanting f (I/I) impurity ions into the substrate using the dummy gate as a mask. A pad oxide layer and dielectric layer are formed over the substrate surface. The dielectric layer over the dummy gate is removed preferably by a CMP process. We then remove the dummy gate to form a gate opening exposing the substrate surface. A gate dielectric layer is formed over the substrate surface in the gate opening. We form a polysilicon layer over the dielectric layer and the substrate surface in the gate opening. The polysilicon layer is patterned to form a T-gate. The dielectric layer is removed. We forming source/drain (S/D) regions adjacent to the T-gate by an Ion implant process. A silicide layer is formed over the T-gate and the substrate to form silicide contacts to the SID regions and gate contacts to the T-gate. Then we form a dielectric layer (ILD) over the T-gate and substrate. We form contact opening through the dielectric layer to expose the S/D regions and T-gate. We form contacts to the S/D regions and to the T-gate.

摘要翻译： 一种用于T栅极和自对准硅化物工艺的方法，其允许窄的底栅宽度低于0.25μm和宽的顶栅宽度以允许在T栅极的顶部上的硅化物栅极接触。 在衬底上形成由绝缘材料构成的虚拟栅极。 然后，使用伪栅极作为掩模，优选通过将f（I / I）杂质离子注入到衬底中来形成与虚拟栅极相邻的LDD区域。 在衬底表面上形成衬垫氧化物层和电介质层。 虚拟栅极上的电介质层优选地通过CMP工艺去除。 然后我们去除虚拟栅极以形成露出衬底表面的栅极开口。 在栅极开口中的衬底表面上形成栅极电介质层。 我们在电介质层和栅极开口中的衬底表面上形成多晶硅层。 图案化多晶硅层以形成T形栅极。 去除电介质层。 我们通过离子注入工艺形成与T型栅极相邻的源极/漏极（S / D）区域。 在T栅极和衬底之上形成硅化物层，以形成与SID区的硅化物接触和到T栅极的栅极接触。 然后我们在T栅极和衬底上形成介电层（ILD）。 我们通过介电层形成接触开口以暴露S / D区域和T型栅极。 我们与S / D区域和T型门形成联系。

公开(公告)号：US20050130402A1

公开(公告)日：2005-06-16

申请号：US11045202

申请日：2005-01-27

申请人： Yelehanka Ramachandramurthy Pradeep ,  Tong Chen ,  Zhi Han ,  Zhen Zheng ,  Kelvin Ong ,  Tian Gu ,  Syn Cheah

发明人： Yelehanka Ramachandramurthy Pradeep ,  Tong Chen ,  Zhi Han ,  Zhen Zheng ,  Kelvin Ong ,  Tian Gu ,  Syn Cheah

IPC分类号： H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/4763 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L21/823468 ,  H01L21/823475 ,  H01L29/6656

摘要： An integrated circuit is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spacer and a liner is formed under the spacer. A first dielectric layer is formed over the semiconductor substrate, the shaped spacer, the spacer, the liner, and the gate. A second dielectric layer is formed over the first dielectric layer. A local interconnect opening is formed in the second dielectric layer down to the first dielectric layer. The local interconnect opening in the first dielectric layer is opened to expose the junction in the semiconductor substrate and the first gate. The local interconnect openings in the first and second dielectric layers are filled with a conductive material.

摘要翻译： 提供集成电路。 分别在半导体衬底上和上方提供栅极电介质和栅极。 在栅极电介质附近形成接合部，并且在栅极周围形成成形间隔物。 间隔件形成在成形间隔件下方，衬垫形成在间隔件下方。 第一电介质层形成在半导体衬底，成形间隔物，间隔物，衬垫和栅极上。 在第一电介质层上形成第二电介质层。 局部互连开口形成在第二电介质层中，直到第一电介质层。 打开第一介电层中的局部互连开口以暴露半导体衬底和第一栅极中的结。 第一和第二介电层中的局部互连开口用导电材料填充。

公开(公告)号：US06355581B1

公开(公告)日：2002-03-12

申请号：US09511276

申请日：2000-02-23

申请人： Vladislav Vassiliev ,  John Leonard Sudijono ,  Yelehanka Ramachandramurthy Pradeep ,  Jie Yu

发明人： Vladislav Vassiliev ,  John Leonard Sudijono ,  Yelehanka Ramachandramurthy Pradeep ,  Jie Yu

IPC分类号： H01L21316

CPC分类号： H01L21/02274 ,  C23C16/045 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02129 ,  H01L21/02131 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/31612 ,  H01L21/31625 ,  H01L21/31629

摘要： A method for fabricating a silicon oxide and silicon glass layers at low temperature using High Density Plasma CVD with silane or inorganic or organic silane derivatives as a source of silicon, inorganic compounds containing boron, phosphorus, and fluorine as a doping compounds, oxygen, and gas additives is described. RF plasma with certain plasma density is maintained throughout the entire deposition step in reactor chamber. Key feature of the invention's process is a silicon source to gas additive mole ratio, which is maintained depending on the used compound and deposition process conditions. Inorganic halide-containing compounds are used as gas additives. This feature provides the reaction conditions for the proper reaction performance that allows a deposition of a film with. good film integrity and void-free gap-fill within the steps of device structures.

摘要翻译： 一种使用硅烷或无机或有机硅烷衍生物作为硅源的高密度等离子体CVD制备低温氧化硅和硅玻璃层的方法，含有硼，磷和氟的无机化合物作为掺杂化合物，氧和 描述了气体添加剂。 在反应器室中的整个沉积步骤中保持具有一定等离子体密度的RF等离子体。 本发明方法的主要特征是硅源与气体添加剂的摩尔比，其依赖于使用的化合物和沉积工艺条件而保持。 使用无机卤化物作为气体添加剂。 该特征提供了允许膜沉积的适当反应性能的反应条件。 良好的薄膜完整性和在设备结构的步骤内无空隙间隙填充。

公开(公告)号：US06251764B1

公开(公告)日：2001-06-26

申请号：US09439368

申请日：1999-11-15

申请人： Yelehanka Ramachandramurthy Pradeep ,  Jie Yu ,  Guan Ping Wu

发明人： Yelehanka Ramachandramurthy Pradeep ,  Jie Yu ,  Guan Ping Wu

IPC分类号： H01L213205

CPC分类号： H01L21/31116 ,  H01L21/3185 ,  H01L21/76832 ,  H01L21/76834 ,  H01L29/6659

摘要： A new method of forming silicon nitride sidewall spacers has been achieved. This method is used to fabricate tapered, L-shaped spacer profiles using a two-step etching process that can be performed insitu. In accordance with the objects of this invention, a new method of forming silicon nitride sidewall spacers has been achieved. An isolation region is provided overlying a semiconductor substrate. Conductive traces are provided overlying the insulator layer. A liner oxide layer is deposited overlying the conductive traces and the insulator layer. A silicon nitride layer is deposited overlying the liner oxide layer. The silicon nitride layer is anisotropically etched down to reduce the vertical thickness of the silicon nitride layer while not exposing the underlying liner oxide layer. The silicon nitride layer is etched through to form silicon nitride sidewall spacers adjacent to the conductive traces. This etching through results in a tapered, L-shaped sidewall profile, and the integrated circuit device is completed.

摘要翻译： 已经实现了形成氮化硅侧壁间隔物的新方法。 该方法用于使用可以在本发明中进行的两步蚀刻工艺来制造锥形的L形间隔件型材。 根据本发明的目的，已经实现了形成氮化硅侧壁间隔物的新方法。 设置在半导体衬底上的隔离区域。 导电迹线被覆盖在绝缘体层上。 衬底氧化层沉积在导电迹线和绝缘体层上。 沉积覆盖衬垫氧化物层的氮化硅层。 氮化硅层被各向异性地向下蚀刻以减小氮化硅层的垂直厚度，同时不暴露下面的衬里氧化物层。 蚀刻氮化硅层以形成邻近导电迹线的氮化硅侧壁间隔物。 该蚀刻导致锥形的L形侧壁轮廓，并且集成电路器件完成。

公开(公告)号：US06200887B1

公开(公告)日：2001-03-13

申请号：US09490133

申请日：2000-01-24

申请人： Palanivel Balasubramaniam ,  Narayanan Balasubramanian ,  Yelehanka Ramachandramurthy Pradeep ,  Arjun Kantimahanti

发明人： Palanivel Balasubramaniam ,  Narayanan Balasubramanian ,  Yelehanka Ramachandramurthy Pradeep ,  Arjun Kantimahanti

IPC分类号： H01L214763

CPC分类号： H01L21/28105 ,  H01L21/28123 ,  H01L21/28247 ,  H01L21/31662

摘要： A method for forming gate structures with smooth sidewalls by amorphizing the polysilicon along the gate boundaries is described. This method results in minimal gate depletion effects and improved critical dimension control in the gates of smaller devices. The method involves providing a gate silicon oxide layer on the surface of the semiconductor substrate. A gate electrode layer, such as polysilicon is deposited over the gate silicon oxide followed by a masking oxide layer deposited over the gate electrode layer. The masking oxide layer is patterned for the formation of the gate electrode. An ion implantation of silicon or germanium amorphizes the area of the polysilicon not protected by the masking oxide mask and also amorphizes the area along the boundaries of the polysilicon gate. Thereafter, the amorphized silicon is then removed by an anisotropic etch leaving a narrow area of amorphized silicon on the gate electrode sidewalls under the edges of the masking oxide mask completing the gate structure having smooth sidewalls.

摘要翻译： 描述了通过沿着栅极边界使多晶硅非晶化来形成具有平滑侧壁的栅极结构的方法。 这种方法导致最小的栅极耗尽效应和较小器件的栅极中的改进的临界尺寸控制。 该方法包括在半导体衬底的表面上提供栅极氧化硅层。 在栅极氧化硅上沉积诸如多晶硅的栅极电极层，随后沉积在栅极电极层上的掩模氧化物层。 图案化掩模氧化物层以形成栅电极。 硅或锗的离子注入对未被掩模氧化物掩模保护的多晶硅区域进行非晶化，并且使沿多晶硅栅极边界的区域非晶化。 此后，通过各向异性蚀刻去除非晶化硅，在掩模氧化物掩模的边缘下方的栅极电极侧壁上留下非晶形硅的窄区域，从而完成具有平滑侧壁的栅极结构。

公开(公告)号：US06660642B2

公开(公告)日：2003-12-09

申请号：US09912623

申请日：2001-07-25

申请人： Zou Zheng ,  Zhou Mei Sheng ,  Yelehanka Ramachandramurthy Pradeep ,  Paul Proctor

发明人： Zou Zheng ,  Zhou Mei Sheng ,  Yelehanka Ramachandramurthy Pradeep ,  Paul Proctor

IPC分类号： H01L21302

CPC分类号： H01L21/3065

摘要： A novel method to remove residual toxic gases trapped by a polymerizing process by an inert ion sputter is described. A masking layer is formed overlying a semiconductor substrate. An opening is etched through the masking layer into the semiconductor substrate whereby a polymer forms on sidewalls of the opening and whereby residual toxic gas reactants from gases used in the etching step are adsorbed by the polymer. Thereafter, the polymer is sputtered with non-reactive ions whereby the residual toxic gas reactants are desorbed from the polymer to complete removal of residual toxic gas reactants in the fabrication of an integrated circuit device.