公开(公告)号：US10269812B1

公开(公告)日：2019-04-23

申请号：US15814724

申请日：2017-11-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Lars Liebmann ,  Daniel Chanemougame ,  Chanro Park ,  John H. Zhang ,  Steven Bentley ,  Hui Zang

IPC: H01L27/112 ,  H01L29/10 ,  H01L21/8234 ,  H01L27/24 ,  H01L29/78 ,  H01L29/808 ,  H01L45/00 ,  H01L29/66 ,  H01L29/06 ,  H01L23/522 ,  H01L21/02

Abstract: A first vertical field effect transistor (VFET) and a second VFET are formed on a substrate. The VFETs are parallel and adjacent to one another, and each comprises: a fin-shaped semiconductor; a lower source/drain (S/D) element; an upper S/D element; and a gate conductor. A portion of a gate conductor of the second VFET that is positioned over a lower S/D element of the second VFET is removed to leave a trench. An isolation spacer is formed to contact the gate conductor of the second VFET in a first portion of the trench. A lower S/D contact of the second VFET is formed on the lower S/D element of the second VFET in a second portion of the trench, a lower S/D contact of the first VFET is formed to a lower S/D element of the first VFET, and contacts are formed.

公开(公告)号：US20190056651A1

公开(公告)日：2019-02-21

申请号：US15681491

申请日：2017-08-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Erik Verduijn ,  Yulu Chen ,  Lars Liebmann ,  Pawitter Mangat

IPC: G03F1/24 ,  G03F1/72 ,  G03F1/84 ,  G03F7/40 ,  H01L21/033 ,  H01L21/3213

Abstract: A photomask includes a substrate having a top surface. A topographical feature is formed on the top surface of the substrate. The topographical feature may be a bump or a pit created on the top surface of the substrate. A reflector is formed on the top surface of the substrate over the topographical feature. The topographical feature warps the reflector in order to generate phase and/or amplitude gradients in light reflected off the reflector. An absorber is patterned on the reflector defining lithographic patterns for a resist material. The gradients in the light reflected off the reflector create shadow regions during lithography of the resist material using extreme ultraviolet (EUV) light.

公开(公告)号：US10211100B2

公开(公告)日：2019-02-19

申请号：US15469701

申请日：2017-03-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Lars Liebmann ,  Nigel Cave ,  Andre Labonte ,  Nicholas LiCausi ,  Guillaume Bouche ,  Chanro Park

IPC: H01L21/764 ,  H01L21/768

Abstract: One method includes performing an etching process to define a gate cavity that exposes an upper surface and at least a portion of the sidewalls of a gate structure and forming a replacement spacer structure adjacent the exposed sidewalls of the gate structure, wherein the replacement spacer structure exposes a portion of the upper surface of the gate structure and includes at least one air space. In this example, the method also includes forming a conformal etch stop layer and a replacement gate cap structure in the gate cavity, selectively removing a portion of the replacement gate cap structure and a portion of the conformal etch stop layer so as to thereby expose the upper surface of the gate structure, and forming a conductive gate contact structure (CB) in the conductive gate contact opening, wherein the entire conductive gate contact structure (CB) is positioned vertically above the active region.

公开(公告)号：US10192819B1

公开(公告)日：2019-01-29

申请号：US15814435

申请日：2017-11-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel Chanemougame ,  Lars Liebmann ,  Ruilong Xie

IPC: H01L29/00 ,  H01L23/50 ,  H01L25/07 ,  H01L29/417 ,  H01L21/8234

Abstract: Disclosed are integrated circuit (IC) structure embodiments that incorporate a stacked pair of field effect transistors (FETs) (e.g., gate-all-around FETs) and metal components that enable power and/or signal connections to source/drain regions of those FETs. Specifically, the IC includes a first FET and a second FET stacked on and sharing a gate with the first FET. The metal components include an embedded contact in a source/drain region of the first FET and connected to a wire (e.g., a power or signal wire). The wire can be a front end of the line (FEOL) wire positioned laterally adjacent to the source/drain region and the embedded contact can extend laterally from the source/drain region to the FEOL wire. Alternatively, the wire can be a back end of the line (BEOL) wire and an insulated contact can extend vertically from the embedded contact through the second FET to the BEOL wire.

公开(公告)号：US20180277430A1

公开(公告)日：2018-09-27

申请号：US15469701

申请日：2017-03-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Lars Liebmann ,  Nigel Cave ,  Andre Labonte ,  Nicholas LiCausi ,  Guillaume Bouche ,  Chanro Park

IPC: H01L21/768 ,  H01L21/764

CPC classification number: H01L21/76879 ,  H01L21/764 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/7685

Abstract: One method includes performing an etching process to define a gate cavity that exposes an upper surface and at least a portion of the sidewalls of a gate structure and forming a replacement spacer structure adjacent the exposed sidewalls of the gate structure, wherein the replacement spacer structure exposes a portion of the upper surface of the gate structure and includes at least one air space. In this example, the method also includes forming a conformal etch stop layer and a replacement gate cap structure in the gate cavity, selectively removing a portion of the replacement gate cap structure and a portion of the conformal etch stop layer so as to thereby expose the upper surface of the gate structure, and forming a conductive gate contact structure (CB) in the conductive gate contact opening, wherein the entire conductive gate contact structure (CB) is positioned vertically above the active region.

公开(公告)号：US20180182757A1

公开(公告)日：2018-06-28

申请号：US15862064

申请日：2018-01-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Andreas Knorr ,  Murat Kerem Akarvardar ,  Lars Liebmann ,  Nigel Graeme Cave

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/45 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/785 ,  H01L2029/7858

Abstract: Disclosed are methods of forming improved fin-type field effect transistor (FINFET) structures and, particularly, relatively tall single-fin FINFET structures that provide increased drive current over conventional single-fin FINFET structures. The use of such a tall single-fin FINFET provides significant area savings over a FINFET that requires multiple semiconductor fins to achieve the same amount of drive current. Furthermore, since only a single fin is used, only a single leakage path is present at the bottom of the device. Thus, the disclosed FINFET structures can be incorporated into a cell in place of multi-fin FINFETs in order to allow for cell height scaling without violating critical design rules or sacrificing performance.

公开(公告)号：US20180082852A1

公开(公告)日：2018-03-22

申请号：US15271511

申请日：2016-09-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Min Gyu Sung ,  Nigel G. Cave ,  Lars Liebmann

IPC: H01L21/308 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/3065

CPC classification number: H01L21/3088 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L29/1037 ,  H01L29/66795 ,  H01L29/7851

Abstract: Methods for fabricating fins for a fin-type field-effect transistor (FinFET) and fin structures for a FinFET. A conformal layer is formed that includes respective first portions on sidewalls of first hardmask sections previously formed on a substrate, a recess between the first portions on the sidewalls of each adjacent pair of the first hardmask sections, and a second portion between the substrate and the recess. The conformal layer is constituted by a second material chosen to etch selectively to the first material constituting the first hardmask sections. A spacer is formed in each recess and masks the respective second portion of the conformal layer. The conformal layer is then etched to form second hardmask sections each comprised of one of the second portions of the conformal layer. The substrate is etched with the first and second hardmask sections masking the substrate to form a plurality of fins.

公开(公告)号：US09812324B1

公开(公告)日：2017-11-07

申请号：US15405789

申请日：2017-01-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Zhuang ,  Lars Liebmann ,  Stuart A. Sieg ,  Fee Li Lie ,  Mahender Kumar ,  Shreesh Narasimha ,  Ahmed Hassan ,  Guillaume Bouche ,  Xintuo Dai

IPC: H01L21/02 ,  H01L21/76 ,  H01L21/30 ,  H01L21/027 ,  H01L29/66 ,  H01L27/02 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/308 ,  H01L21/28 ,  H01L21/3065

CPC classification number: H01L27/0207 ,  H01L21/28123 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823431 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method includes providing a semiconductor structure having a substrate including a longitudinally extending plurality of fins formed thereon. A target layout pattern is determined, which overlays active areas devices disposed on the fins. The target layout pattern includes a first group of sections overlaying devices having more fins than adjacent devices and a second group of sections overlaying devices having less fins than adjacent devices. A first extended exposure pattern is patterned into the structure, and includes extensions that extend sections of the first group toward adjacent sections of the first group. A second extended exposure pattern is patterned into the structure, and includes extensions that extend sections of the second group toward adjacent sections of the second group. Portions of the first and second extended exposure patterns are combined to form a final pattern overlaying the same active areas as the target pattern.