公开(公告)号：US20170047253A1

公开(公告)日：2017-02-16

申请号：US14822340

申请日：2015-08-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Ruilong Xie ,  Min Gyu Sung ,  Hoon Kim

IPC: H01L21/768 ,  H01L21/311 ,  H01L29/66 ,  H01L27/088 ,  H01L29/40 ,  H01L29/417 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/3105

CPC classification number: H01L21/76897 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02362 ,  H01L21/31051 ,  H01L21/31055 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76837 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/401 ,  H01L29/41758 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2221/1026 ,  H01L2221/1036

Abstract: One illustrative method disclosed includes, among other things, forming a silicon dioxide etch stop layer on and in contact with a source/drain region and adjacent silicon nitride sidewall spacers positioned on two laterally spaced-apart transistors having silicon dioxide gate cap layers, performing a first etching process through an opening in a layer of insulating material to remove the silicon nitride material positioned above the source/drain region, performing a second etching process to remove a portion of the silicon dioxide etch stop layer and thereby expose a portion of the source/drain region, and forming a conductive self-aligned contact that is conductively coupled to the source/drain region.

Abstract translation: 所公开的一种示例性方法包括在源极/漏极区域上形成二氧化硅蚀刻停止层并与源极/漏极区域接触的相邻的氮化硅侧壁间隔物，其位于具有二氧化硅栅极盖层的两个横向间隔开的晶体管上， 通过绝缘材料层中的开口进行第一蚀刻工艺，以去除位于源/漏区域上方的氮化硅材料，执行第二蚀刻工艺以去除二氧化硅蚀刻停止层的一部分，从而暴露出源的一部分 /漏极区域，并且形成导电地与源极/漏极区域耦合的导电自对准接触。

公开(公告)号：US20160351411A1

公开(公告)日：2016-12-01

申请号：US14726712

申请日：2015-06-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Min Gyu Sung ,  Catherine B. Labelle

IPC: H01L21/306 ,  H01L21/311 ,  H01L21/308

CPC classification number: H01L21/3086 ,  H01L21/3083

Abstract: One illustrative method disclosed herein includes, among other things, forming a fin-removal masking layer comprised of a plurality of line-type features, each of which is positioned above one of the fins, and a masking material positioned at least between adjacent features of the fin-removal masking layer and above portions of an insulating material in the trenches between the fins. The method also includes performing an anisotropic etching process through the fin-removal masking layer to remove the portions of the fins to be removed.

Abstract translation: 本文公开的一种说明性方法除其他外包括形成由多个线型特征组成的鳍去除掩模层，每个线型特征位于其中一个翅片上方，并且掩蔽材料至少位于相邻特征之间 翅片去除掩模层和鳍片之间的沟槽中的绝缘材料的上述部分。 该方法还包括通过散热器去除掩模层进行各向异性蚀刻工艺，以除去待除去的散热片的部分。

公开(公告)号：US09449881B1

公开(公告)日：2016-09-20

申请号：US14710053

申请日：2015-05-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L21/311 ,  H01L21/308 ,  H01L21/764 ,  H01L21/762 ,  H01L21/3105 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/823821 ,  H01L29/66795 ,  H01L29/6681

Abstract: A method includes forming a plurality of fins above a substrate, forming at least one dielectric material above and between the plurality of fins, and forming a mask layer above the dielectric material. The mask layer has an opening defined therein. At least one etching process is performed to remove a portion of the at least one dielectric material exposed by the opening so as to expose a top surface portion and sidewall surface portions of at least one fin in the plurality of fins. The at least one dielectric material remains above the substrate adjacent the at least one fin. An etching process is performed to remove the at least one fin.

Abstract translation: 一种方法包括在衬底上形成多个翅片，在多个翅片之上和之间形成至少一种电介质材料，并在电介质材料之上形成掩模层。 掩模层具有限定在其中的开口。 执行至少一个蚀刻工艺以去除由开口暴露的至少一个介电材料的一部分，以暴露多个翅片中的至少一个翅片的顶表面部分和侧壁表面部分。 所述至少一个介电材料保留在与所述至少一个翅片相邻的衬底上。 进行蚀刻处理以去除至少一个翅片。

公开(公告)号：US09412616B1

公开(公告)日：2016-08-09

申请号：US14942448

申请日：2015-11-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Kwan-Yong Lim ,  Min Gyu Sung ,  Ryan Ryoung-Han Kim

IPC: H01L21/00 ,  H01L21/3105 ,  H01L21/027 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/283 ,  H01L21/762

CPC classification number: H01L29/66545 ,  H01L21/76224 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: One illustrative method disclosed herein includes, among other things, forming a multi-layer patterned masking layer comprised of first and second layers of material and first and second openings that extend through both of the first and second layers of material, wherein the first opening is positioned above a first area of the substrate where the DDB isolation structure will be formed and the second opening is positioned above a second area of the substrate where the SDB isolation structure will be formed. The method also includes performing a first process operation through the first opening to form the DDB isolation structure, performing a second process operation to remove the second layer of material and to expose the first opening in the first layer of material, and performing a third process operation through the second opening to form the SDB isolation structure.

Abstract translation: 本文公开的一种说明性方法包括形成由第一和第二层材料构成的多层图案化掩模层，以及延伸穿过第一和第二材料层的第一和第二开口，其中第一开口是 位于基板的将形成DDB隔离结构的第一区域之上，并且第二开口位于衬底的将形成SDB隔离结构的第二区域之上。 该方法还包括通过第一开口执行第一处理操作以形成DDB隔离结构，执行第二处理操作以去除第二层材料并露出第一层材料中的第一开口，以及执行第三工艺 通过第二次开启操作形成SDB隔离结构。

公开(公告)号：US09391174B1

公开(公告)日：2016-07-12

申请号：US14730735

申请日：2015-06-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Ruilong Xie ,  Chanro Park ,  Hoon Kim

IPC: H01L29/66 ,  H01L21/306 ,  H01L21/31 ,  H01L21/311

CPC classification number: H01L29/66795 ,  H01L21/3083

Abstract: Uniform fin recessing for the situation of recessing nonadjacent fins and the situation of recessing adjacent fins includes providing a starting semiconductor structure, the structure including a semiconductor substrate, multiple fins coupled to the substrate, each fin having a hard mask layer thereover and being surrounded by isolation material. The hard mask layer is then removed over some of the fins, at least partially removing the some of the raised structures, the at least partially removing creating openings, and filling the openings with an optical planarization layer (OPL) material.

Abstract translation: 针对不相邻散热片的凹陷状况的均匀的翅片凹陷以及相邻散热片的凹陷情况包括提供起始半导体结构，该结构包括半导体衬底，耦合到衬底的多个鳍片，每个散热片具有其上的硬掩模层并被 隔离材料。 然后在一些翅片上去除硬掩模层，至少部分地去除一些凸起结构，至少部分去除创建开口，并用光学平坦化层（OPL）材料填充开口。

公开(公告)号：US20160163585A1

公开(公告)日：2016-06-09

申请号：US14674460

申请日：2015-03-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung ,  Hoon Kim ,  Andre Labonte

IPC: H01L21/768 ,  H01L29/45 ,  H01L29/417 ,  H01L21/283 ,  H01L29/66

CPC classification number: H01L21/76843 ,  H01L21/283 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66628

Abstract: One method disclosed includes, among other things, forming a structure comprised of an island of a first insulating material positioned between the gate structures above the source/drain region and under a masking layer feature of a patterned masking layer, forming a liner layer that contacts the island of insulating material and the masking layer feature, selectively removing the masking layer feature to thereby form an initial opening that is defined by the liner layer, performing at least one isotropic etching process through the initial opening to remove the island of first insulating material and thereby define a contact opening that exposes the source/drain region, and forming a conductive contact structure in the contact opening that is conductively coupled to the source/drain region.

Abstract translation: 所公开的一种方法包括形成由位于源/漏区之上的栅极结构之间的第一绝缘材料的岛和图案化掩模层的掩模层特征之下的一个结构，形成接触 绝缘材料岛和掩模层特征，选择性地去除掩模层特征，从而形成由衬里层限定的初始开口，通过初始开口进行至少一个各向同性蚀刻工艺以去除第一绝缘材料岛 从而限定暴露源极/漏极区域的接触开口，以及在与源极/漏极区域导电耦合的接触开口中形成导电接触结构。

公开(公告)号：US09362377B1

公开(公告)日：2016-06-07

申请号：US14633998

申请日：2015-02-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hoon Kim ,  Vimal Kamineni ,  Min Gyu Sung ,  Chanro Park

IPC: H01L21/44 ,  H01L23/52 ,  H01L29/49 ,  H01L21/28 ,  H01L21/285 ,  H01L21/321 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/321 ,  H01L21/32134 ,  H01L29/42376 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: Methods for forming a semiconductor gate electrode with a reflowed Co layer and the resulting device are disclosed. Embodiments include forming a trench in an ILD on a substrate; forming a high-k dielectric layer, a WF layer, and a Co layer sequentially on sidewall and bottom surfaces of the trench; reflowing a portion of the Co layer from the WF layer on the sidewall surfaces of the trench to the WF layer on the bottom surface of the trench; removing a remainder of the Co layer from the WF layer on the sidewall surfaces of the trench, above an upper surface of the reflowed Co; recessing the WF layer to the upper surface of the reflowed Co layer, forming a cavity above the reflowed Co layer; and filling the cavity with metal to form a gate electrode.

Abstract translation: 公开了用于形成具有回流Co层的半导体栅电极的方法和所得到的器件。 实施例包括在衬底上形成ILD中的沟槽; 在沟槽的侧壁和底表面上依次形成高k电介质层，WF层和Co层; 将Co层的一部分从沟槽的侧壁表面上的WF层回流到沟槽的底表面上的WF层; 从所述沟槽的侧壁表面上的所述WF层中除去所述Co层的剩余部分，在所述回流Co的上表面上方; 将WF层凹陷到回流Co层的上表面，在回流Co层上方形成空腔; 并用金属填充空腔以形成栅电极。

公开(公告)号：US20160049399A1

公开(公告)日：2016-02-18

申请号：US14865784

申请日：2015-09-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Hoon Kim ,  Min Gyu Sung

IPC: H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L29/423

CPC classification number: H01L27/0922 ,  H01L21/28026 ,  H01L21/2807 ,  H01L21/283 ,  H01L21/82345 ,  H01L21/823456 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0928 ,  H01L27/105 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/4958 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/772 ,  H01L29/7833 ,  H01L29/785

Abstract: One illustrative gate structure of a transistor device disclosed herein includes a high-k gate insulation layer and a work function metal layer positioned on the high-k gate insulation layer. The device further includes a first bulk metal layer positioned on the work function metal layer. The device further includes a second bulk metal layer. The first and second bulk metal layers have upper surfaces that are at substantially the same height level, and the first and second bulk metal layers are made of substantially the same material. The device further includes a conductive etch stop layer between the first and second bulk metal layers.

Abstract translation: 本文公开的晶体管器件的一个说明性栅极结构包括高k栅极绝缘层和位于高k栅极绝缘层上的功函数金属层。 该装置还包括位于功函数金属层上的第一体金属层。 该装置还包括第二体金属层。 第一和第二块体金属层具有基本上相同的高度水平的上表面，并且第一和第二块体金属层由基本上相同的材料制成。 该器件还包括在第一和第二块体金属层之间的导电蚀刻停止层。

公开(公告)号：US20150364378A1

公开(公告)日：2015-12-17

申请号：US14301748

申请日：2014-06-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  William J. Taylor, JR. ,  Min Gyu Sung

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L21/28

CPC classification number: H01L29/41783 ,  H01L21/28008 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823828 ,  H01L21/823871 ,  H01L27/088 ,  H01L29/0653

Abstract: One method disclosed herein includes forming an opening in a layer of material so as to expose the source/drain regions of a transistor and a first portion of a gate cap layer positioned above an active region, reducing the thickness of a portion of the gate cap layer positioned above the isolation region, defining separate initial source/drain contacts positioned on opposite sides of the gate structure, performing a common etching process sequence to define a gate contact opening that extends through the reduced-thickness portion of the gate cap layer and a plurality of separate source/drain contact openings in the layer of insulating material, and forming a conductive gate contact structure and conductive source/drain contact structures.

Abstract translation: 本文公开的一种方法包括在材料层中形成开口以暴露晶体管的源极/漏极区域和位于有源区域上方的栅极覆盖层的第一部分，从而减小栅极帽部分的厚度 位于隔离区域上方的层，限定位于栅极结构的相对侧上的单独的初始源极/漏极触点，执行公共蚀刻工艺序列以限定延伸穿过栅极盖层的厚度减小的部分的栅极接触开口，以及 绝缘材料层中的多个独立的源极/漏极接触开口，以及形成导电栅极接触结构和导电源极/漏极接触结构。

公开(公告)号：US20150340468A1

公开(公告)日：2015-11-26

申请号：US14283721

申请日：2014-05-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kwan-Yong Lim ,  Min Gyu Sung ,  Jody A. Fronheiser ,  Christopher M. Prindle

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785

Abstract: A method includes forming at least one fin in a semiconductor substrate. A sacrificial gate structure is formed around a first portion of the at least one fin. Sidewall spacers are formed adjacent the sacrificial gate structure. The sacrificial gate structure and spacers expose a second portion of the at least one fin. An epitaxial material is formed on the exposed second portion. At least one process operation is performed to remove the sacrificial gate structure and thereby define a gate cavity between the spacers that exposes the first portion of the at least one fin. The first portion of the at least one fin is recessed to a first height less than a second height of the second portion of the at least one fin. A replacement gate structure is formed within the gate cavity above the recessed first portion of the at least one fin.

Abstract translation: 一种方法包括在半导体衬底中形成至少一个翅片。 在所述至少一个翅片的第一部分周围形成牺牲栅极结构。 侧壁间隔件形成在牺牲栅极结构附近。 所述牺牲栅极结构和间隔物暴露所述至少一个翅片的第二部分。 在暴露的第二部分上形成外延材料。 执行至少一个处理操作以去除牺牲栅极结构，从而在间隔件之间限定暴露至少一个鳍片的第一部分的栅极腔。 所述至少一个翅片的第一部分凹陷到小于所述至少一个翅片的第二部分的第二高度的第一高度。 在所述至少一个翅片的凹入的第一部分上方的栅极空腔内形成替换栅极结构。