中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

50 records (took 0.02 seconds)

    Flexible disposable MEMS pressure sensor
    41.
    发明授权
    Flexible disposable MEMS pressure sensor 有权

    公开(公告)号：US10479677B2

    公开(公告)日：2019-11-19

    申请号：US15535327

    申请日：2015-12-10

    Applicant: Robert Bosch GmbH ,  Seow Yuen Yee ,  Gary Yama

    Inventor： Seow Yuen Yee ,  Gary Yama

    IPC: B81C99/00 ,  G01L9/00 ,  B81B7/00 ,  G01L19/14

    Abstract: A MEMS device, e.g., a flexible MEMS pressure sensor, is formed by disposing a sacrificial layer, such as photoresist, on a substrate. A first flexible support layer is disposed on the substrate, and a first conductive layer is disposed over a portion of the first support layer. A liquid or gel separator, e.g., silicone oil, is disposed on an internal region of the first conductive layer. A second flexible support layer encapsulates the first conductive layer and the separator. A second conductive layer disposed over the second support layer at least partially overlaps the first conductive layer and forms a parallel plate capacitor. A third flexible support layer encapsulates the second conductive layer and second support layer. Soaking the sensor in hot water releases the sensor from the sacrificial layer.

    Wafer with recessed plug
    44.
    发明授权
    Wafer with recessed plug 有权

    公开(公告)号：US08647930B2

    公开(公告)日：2014-02-11

    申请号：US13232268

    申请日：2011-09-14

    Applicant: Andrew B. Graham ,  Gary Yama ,  Gary O'Brien

    Inventor： Andrew B. Graham ,  Gary Yama ,  Gary O'Brien

    IPC: H01L21/00 ,  H01L21/84

    CPC classification number: B81B7/00 ,  B81B2203/0307 ,  B81C1/00126 ,  H01L21/76283

    Abstract: In one embodiment, a method of forming a plug includes providing a base layer, providing an intermediate oxide layer above an upper surface of the base layer, providing an upper layer above an upper surface of the intermediate oxide layer, etching a trench including a first trench portion extending through the upper layer, a second trench portion extending through the oxide layer, and a third trench portion extending into the base layer, depositing a first material portion within the third trench portion, depositing a second material portion within the second trench portion, and depositing a third material portion within the first trench portion.

    Device formed using a hard mask and etch stop layer
    46.
    发明授权
    Device formed using a hard mask and etch stop layer 有权
    使用硬掩模和蚀刻停止层形成的器件

    公开(公告)号：US08232143B2

    公开(公告)日：2012-07-31

    申请号：US13171112

    申请日：2011-06-28

    Applicant: Gary Yama

    Inventor： Gary Yama

    IPC: H01L21/44

    CPC classification number: B81C1/00595 ,  B81C2201/0132 ,  B81C2201/014 ,  H01L21/0475

    Abstract: A method of etching a device in one embodiment includes providing a silicon carbide substrate, forming a silicon nitride layer on a surface of the silicon carbide substrate, forming a silicon carbide layer on a surface of the silicon nitride layer, forming a silicon dioxide layer on a surface of the silicon carbide layer, forming a photoresist mask on a surface of the silicon dioxide layer, and etching the silicon dioxide layer through the photoresist mask.

    Abstract translation: 在一个实施例中蚀刻器件的方法包括提供碳化硅衬底，在碳化硅衬底的表面上形成氮化硅层，在氮化硅层的表面上形成碳化硅层，在二氧化硅层上形成二氧化硅层 碳化硅层的表面，在二氧化硅层的表面上形成光致抗蚀剂掩模，并且通过光致抗蚀剂掩模蚀刻二氧化硅层。

    Substrate with multiple encapsulated pressures
    47.
    发明授权
    Substrate with multiple encapsulated pressures 有权
    具有多重封装压力的基材

    公开(公告)号：US07875482B2

    公开(公告)日：2011-01-25

    申请号：US12407639

    申请日：2009-03-19

    Applicant: Robert N. Candler ,  Gary Yama

    Inventor： Robert N. Candler ,  Gary Yama

    IPC: H01L21/00

    CPC classification number: H01L23/3171 ,  B81B7/02 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81C1/00293 ,  B81C2203/0136 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of forming a device with multiple encapsulated pressures is disclosed herein. In accordance with one embodiment of the present invention, there is provided a method of forming a device with multiple encapsulated pressures, including providing a substrate, forming a functional layer on top of a surface of the substrate, the functional layer including a first device portion at a first location, and a second device portion at a second location adjacent to the first location, encapsulating the functional layer, forming at least one diffusion resistant layer above the encapsulated functional layer at a location above the first location and not above the second location, modifying an environment adjacent the at least one diffusion resistant layer, and diffusing a gas into the second location as a result of the modified environment.

    Abstract translation: 本文公开了形成具有多个封装压力的装置的方法。 根据本发明的一个实施例，提供了一种形成具有多个封装压力的器件的方法，包括提供衬底，在衬底的表面的顶部上形成功能层，所述功能层包括第一器件部分 在第一位置处的第二设备部分和与第一位置相邻的第二位置处的第二设备部分，封装功能层，在第一位置上方并且不在第二位置之上的位置处在封装的功能层上方形成至少一个扩散阻挡层 改变邻近所述至少一个扩散阻挡层的环境，以及由于所述改进的环境而将气体扩散到所述第二位置。

    Microelectromechanical devices and fabrication methods
    48.
    发明申请
    Microelectromechanical devices and fabrication methods 有权
    微机电装置及制造方法

    公开(公告)号：US20070042521A1

    公开(公告)日：2007-02-22

    申请号：US11205702

    申请日：2005-08-16

    Applicant: Gary Yama

    Inventor： Gary Yama

    IPC: H01L21/00

    CPC classification number: B81C1/00333

    Abstract: There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a MEMS device, and technique of fabricating or manufacturing a MEMS device, having mechanical structures encapsulated in a chamber prior to final packaging. An embodiment further includes a buried polysilicon layer and a “protective layer” deposited over the buried polysilicon layer to prevent possible erosion of, or damage to the buried polysilicon layer during processing steps. The material that encapsulates the mechanical structures, when deposited, includes one or more of the following attributes: low tensile stress, good step coverage, maintains its integrity when subjected to subsequent processing, does not significantly and/or adversely impact the performance characteristics of the mechanical structures in the chamber (if coated with the material during deposition), and/or facilitates integration with high-performance integrated circuits. In one embodiment, the material that encapsulates the mechanical structures is, for example, silicon (polycrystalline, amorphous or porous, whether doped or undoped), silicon carbide, silicon-germanium, germanium, or gallium-arsenide.

    Abstract translation: 这里描述和说明了许多发明。 在一个方面，本发明涉及MEMS器件，以及制造或制造MEMS器件的技术，其具有在最终封装之前封装在腔室中的机械结构。 实施例还包括沉积在掩埋多晶硅层上的掩埋多晶硅层和“保护层”，以防止在处理步骤期间可能的侵蚀或损坏埋置的多晶硅层。 当沉积时，封装机械结构的材料包括以下属性中的一个或多个：低拉伸应力，良好的阶梯覆盖，在经受后续加工时保持其完整性，不会显着和/或不利地影响 室中的机械结构（如果在沉积期间涂覆材料）和/或促进与高性能集成电路的集成。 在一个实施例中，封装机械结构的材料是例如硅（多晶，无定形或多孔，无论掺杂或未掺杂），碳化硅，硅 - 锗，锗或砷化镓。

    Anti-stiction technique for electromechanical systems and electromechanical device employing same
    49.
    发明申请
    Anti-stiction technique for electromechanical systems and electromechanical device employing same 有权

    公开(公告)号：US20060246631A1

    公开(公告)日：2006-11-02

    申请号：US11115828

    申请日：2005-04-27

    Applicant: Markus Lutz ,  Aaron Partridge ,  Wilhelm Frey ,  Markus Ulm ,  Matthias Metz ,  Brian Stark ,  Gary Yama

    Inventor： Markus Lutz ,  Aaron Partridge ,  Wilhelm Frey ,  Markus Ulm ,  Matthias Metz ,  Brian Stark ,  Gary Yama

    IPC: H01L21/44

    CPC classification number: B81C1/0096 ,  B81B3/0005 ,  B81C2201/112 ,  B82Y30/00 ,  H01L2224/13 ,  H01L2924/1461 ,  H01L2924/00

    Abstract: A mechanical structure is disposed in a chamber, at least a portion of which is defined by the encapsulation structure. A first method provides a channel cap having at least one preform portion disposed over or in at least a portion of an anti-stiction channel to seal the anti-stiction channel, at least in part. A second method provides a channel cap having at least one portion disposed over or in at least a portion of an anti-stiction channel to seal the anti-stiction channel, at least in part. The at least one portion is fabricated apart from the electromechanical device and thereafter affixed to the electromechanical device. A third method provides a channel cap having at least one portion disposed over or in at least a portion of the anti-stiction channel to seal an anti-stiction channel, at least in part. The at least one portion may comprise a wire ball, a stud, metal foil or a solder preform. A device includes a substrate, an encapsulation structure and a mechanical structure. An anti-stiction layer is disposed on at least a portion of the mechanical structure. An anti-stiction channel is formed in at least one of the substrate and the encapsulation structure. A cap has at least one preform portion disposed over or in at least a portion of the anti-stiction channel to seal the anti-stiction channel, at least in part.

    Method for manufacturing a microsystem
    50.
    发明申请
    Method for manufacturing a microsystem 审中-公开
    微系统制造方法

    公开(公告)号：US20050054134A1

    公开(公告)日：2005-03-10

    申请号：US10898114

    申请日：2004-07-22

    Applicant: Wilhelm Frey ,  Silvia Kronmueller ,  Christoph Duenn ,  Gary Yama ,  Jochen Zoellin

    Inventor： Wilhelm Frey ,  Silvia Kronmueller ,  Christoph Duenn ,  Gary Yama ,  Jochen Zoellin

    IPC: B81B7/00 ,  B81C1/00 ,  H01L21/00 ,  H01L21/331 ,  H01L21/8222

    CPC classification number: B81C1/00595 ,  B81C2201/014

    Abstract: A method for manufacturing a microsystem is provided, which microsystem has a first functional layer situated on a substrate provided with an integrated circuit, the first functional layer including a conductive area and a sub-layer, and a second mechanical functional layer situated on the first functional layer. In the manufacturing method, the second mechanical functional layer is first applied to a sacrificial layer situated on the first functional layer and structured. In addition, a protective layer is provided in selected areas on the side of sub-layer facing away from the conductive area, such that as the sacrificial layer is etched, etching of the areas of the first functional layer covered by the protective layer is prevented, and in the areas of the first functional layer without the protective layer, the sub-layer is selectively etched simultaneously with the sacrificial layer, down to the conductive area.

    Abstract translation: 提供了一种用于制造微系统的方法，该微系统具有位于设置有集成电路的基板上的第一功能层，第一功能层包括导电区域和子层，第二机械功能层位于第一 功能层。 在制造方法中，首先将第二机械功能层施加到位于第一功能层上并构成的牺牲层。 此外，在子层背离导电区域的一侧的选定区域中提供保护层，使得当牺牲层被蚀刻时，防止由保护层覆盖的第一功能层的区域的蚀刻 ，并且在没有保护层的第一功能层的区域中，子层与牺牲层同时选择性地蚀刻到导电区域。

Patent Agency Ranking