公开(公告)号：US09824970B1

公开(公告)日：2017-11-21

申请号：US15193300

申请日：2016-06-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xunyuan Zhang ,  Ruilong Xie

IPC: H01L23/528 ,  H01L21/288 ,  H01L27/088 ,  H01L21/768 ,  H01L23/532 ,  H01L21/8234 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L21/288 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76874 ,  H01L21/76879 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53238 ,  H01L27/088

Abstract: Disclosed are methods of forming integrated circuit (IC) structures with hybrid metallization interconnects. A dual damascene process is performed to form trenches in an upper portion of a dielectric layer and contact holes that extend from the trenches to a gate electrode and to contact plugs on source/drain regions. A first metal is deposited into the contact holes by electroless deposition and a second metal is then deposited. Alternatively, a single damascene process is performed to form a first contact hole through a dielectric layer to a gate electrode and a first metal is deposited therein by electroless deposition. Next, a dual damascene process is performed to form trenches in an upper portion of the dielectric layer, including a trench that traverses the first contact hole, and to form second contact holes that extend from the trenches to contact plugs on source/drain regions. A second metal is then deposited.

公开(公告)号：US20170256449A1

公开(公告)日：2017-09-07

申请号：US15062328

申请日：2016-03-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Ruilong Xie ,  Vimal Kamineni

IPC: H01L21/768

CPC classification number: H01L21/76877 ,  H01L21/76802 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/53209 ,  H01L23/53238

Abstract: One illustrative method disclosed herein includes, among other things, forming a first trench and a second trench in a layer of insulating material, the first trench having a first lateral critical dimension, the second trench having a second lateral critical dimension that is greater than the first lateral critical dimension of the first trench, forming a first conductive structure in the first trench, wherein a first bulk metal material constitutes a bulk portion of the first conductive structure, and forming a second conductive structure in the second trench, wherein a second bulk metal material constitutes a bulk portion of the second conductive structure and wherein the first bulk metal material and second bulk metal material are different materials.

公开(公告)号：US09559059B2

公开(公告)日：2017-01-31

申请号：US14526678

申请日：2014-10-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Tibor Bolom ,  Errol Todd Ryan

IPC: H01L21/44 ,  H01L23/535 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L23/485

CPC classification number: H01L23/535 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76864 ,  H01L21/76879 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One illustrative method disclosed herein includes, among other things, forming an opening in a layer of insulating material so as to thereby expose at least a portion of a conductive contact, performing a selective deposition process to selectively form a layer of conductive material in the opening and on the conductive contact, performing an anneal process, depositing at least one conductive material above the selectively formed conductive material layer so as to over-fill the opening, and performing at least one planarization process so as to remove excess materials to thereby define a conductive via that is positioned in the opening and conductively coupled to the conductive contact.

Abstract translation: 本文公开的一种说明性方法包括在绝缘材料层中形成开口，从而暴露至少一部分导电接触，执行选择性沉积工艺以在开口中选择性地形成导电材料层 并且在导电接触上，执行退火工艺，在选择性地形成的导电材料层上方沉积至少一种导电材料，以便过度填充该开口，以及执行至少一个平坦化工艺以便去除多余的材料， 导电通孔，其定位在开口中并且导电地耦合到导电接触。

公开(公告)号：US09530691B1

公开(公告)日：2016-12-27

申请号：US15048280

申请日：2016-02-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xunyuan Zhang ,  Errol Todd Ryan

IPC: H01L21/8242 ,  H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/288 ,  H01L21/66 ,  H01L21/67

CPC classification number: H01L21/76897 ,  H01L21/02142 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02175 ,  H01L21/02244 ,  H01L21/02255 ,  H01L21/288 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/67075 ,  H01L21/67098 ,  H01L21/67253 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76883 ,  H01L22/12 ,  H01L22/20

Abstract: At least one method, apparatus and system disclosed herein for forming an integrated circuit having a dual-orientation self aligned via. A first dielectric layer is formed on a semiconductor substrate. At least one first metal feature is formed in a first metal layer. A first cap feature is deposited over the first metal feature. A manganese silicate etch stop layer is formed above the dielectric layer. An etch process is performed for removing for at least removing the first cap feature. A second metal feature is formed in a second metal layer. A dual-orientation self aligned via connecting a portion of the second metal feature to the first metal feature is formed.

Abstract translation: 本文公开的用于形成具有双向自对准通孔的集成电路的至少一种方法，装置和系统。 第一电介质层形成在半导体衬底上。 在第一金属层中形成至少一个第一金属特征。 第一盖特征被放置在第一金属特征上。 在电介质层上方形成硅酸铝蚀刻停止层。 执行蚀刻处理以移除以至少去除第一盖特征。 在第二金属层中形成第二金属特征。 形成通过将第二金属特征的一部分连接到第一金属特征的双向自对准。

公开(公告)号：US20160358908A1

公开(公告)日：2016-12-08

申请号：US14732038

申请日：2015-06-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Xunyuan Zhang

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L21/76829 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/485 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes, among other things, forming a source/drain contact structure between two spaced-apart transistor gate structures, forming a non-uniform thickness layer of material on the upper surface of the gate cap layers and on the upper surface of the source/drain contact structure, wherein the non-uniform thickness layer of material is thicker above the gate cap layers than it is above the source/drain contact structure, forming an opening in the non-uniform thickness layer of material so as to expose at least a portion of the source/drain contact structure, and forming a V0 via that is conductively coupled to the exposed portion of the source/drain contact structure, the V0 via being at least partially positioned in the opening in the non-uniform thickness layer of material.

Abstract translation: 本文中公开的一种说明性方法包括在两个间隔开的晶体管栅极结构之间形成源极/漏极接触结构，在栅极盖层的上表面上形成不均匀的材料厚度层，并且在上表面 的源极/漏极接触结构，其中材料的不均匀厚度层比栅极盖层之上比源极/漏极接触结构上方更厚，在不均匀厚度的材料层中形成开口，从而 露出源极/漏极接触结构的至少一部分，以及形成通过导电耦合到源/漏接触结构的暴露部分的V0，V0通孔至少部分地定位在开口中的不均匀 材料厚度层。

公开(公告)号：US09299745B2

公开(公告)日：2016-03-29

申请号：US14272916

申请日：2014-05-08

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xunyuan Zhang ,  Sean Xuan Lin ,  Kunaljeet Tanwar

IPC: H01L21/02 ,  H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  H01L43/02

CPC classification number: H01L27/222 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: Integrated circuits with magnetic tunnel junction (MTJ) structures and methods for fabricating integrated circuits with MTJ structures are provided. An exemplary method for fabricating an integrated circuit includes forming a first conductive line in electrical connection with an underlying semiconductor device. The method exposes a surface of the first conductive line. Further, the method selectively deposits a conductive material on the surface of the first conductive line to form an electrode contact. The method includes forming a MTJ structure over the electrode contact.

Abstract translation: 提供了具有磁隧道结（MTJ）结构的集成电路和用于制造具有MTJ结构的集成电路的方法。 用于制造集成电路的示例性方法包括形成与下面的半导体器件电连接的第一导线。 该方法暴露第一导线的表面。 此外，该方法选择性地将导电材料沉积在第一导电线的表面上以形成电极接触。 该方法包括在电极接触件上形成MTJ结构。

公开(公告)号：US09287213B2

公开(公告)日：2016-03-15

申请号：US14695965

申请日：2015-04-24

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xunyuan Zhang ,  Xuan Lin ,  Vimal Kamineni

IPC: H01L21/31 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L23/53266 ,  H01L21/28562 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76849 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits with improved contact structures are provided. In an exemplary embodiment, an integrated circuit includes a semiconductor substrate disposed with a device therein and/or thereon. The integrated circuit includes a contact structure in electrical contact with the device. The contact structure includes a plug metal and a barrier layer, and the barrier layer is selected from fluorine-free tungsten (FFW), tungsten carbide, and tungsten nitride. The integrated circuit further includes a dielectric material overlying the semiconductor substrate. Also, the integrated circuit includes an interconnect formed within the dielectric material and in electrical contact with the contact structure.

Abstract translation: 提供了具有改进的接触结构的集成电路。 在示例性实施例中，集成电路包括在其中和/或其上设置有设备的半导体衬底。 集成电路包括与器件电接触的接触结构。 接触结构包括插塞金属和阻挡层，阻挡层选自无氟钨（FFW），碳化钨和氮化钨。 集成电路还包括覆盖半导体衬底的电介质材料。 此外，集成电路包括形成在电介质材料内并与接触结构电接触的互连。

公开(公告)号：US20150255339A1

公开(公告)日：2015-09-10

申请号：US14201255

申请日：2014-03-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Hoon Kim ,  Christian Witt ,  Larry Zhao

IPC: H01L21/768 ,  H01L21/306

CPC classification number: H01L21/76882 ,  H01L21/30625 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One method includes forming a barrier layer in a trench/opening in an insulating material, forming a first region of a copper material above the barrier layer, forming a metal layer in the trench/opening on the first region of copper material, forming a second region of copper material on the metal layer, performing at least one CMP process to remove any materials positioned above a planarized upper surface of the layer of insulating material outside of the trench/opening so as to thereby define a structure comprised of the metal layer positioned between the first and second regions of copper material, forming a dielectric cap layer above the layer of insulating material and above the structure, and performing a metal diffusion anneal process to form a metal cap layer adjacent at least the upper surface of a conductive copper structure.

Abstract translation: 一种方法包括在绝缘材料的沟槽/开口中形成阻挡层，在阻挡层之上形成铜材料的第一区域，在铜材料的第一区域上的沟槽/开口中形成金属层，形成第二层 在金属层上的铜材料区域，执行至少一个CMP工艺以去除位于沟槽/开口外部的绝缘材料层的平坦化上表面上方的任何材料，从而限定由金属层定位的结构 在铜材料的第一和第二区域之间，在绝缘材料层之上并在结构之上形成电介质盖层，并进行金属扩散退火工艺以形成至少与导电铜结构的上表面相邻的金属盖层 。

公开(公告)号：US09076792B2

公开(公告)日：2015-07-07

申请号：US14287533

申请日：2014-05-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vivian W. Ryan ,  Xunyuan Zhang ,  Paul R. Besser

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/532 ,  H01L21/02 ,  H01L23/538 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L23/53209 ,  H01L21/02697 ,  H01L21/76846 ,  H01L21/76858 ,  H01L21/76873 ,  H01L21/76886 ,  H01L23/53238 ,  H01L23/5384 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a recess defined in a dielectric layer and an interconnect structure defined in the recess. The interconnect structure includes a first barrier layer lining the recess, the first barrier layer including an alloy of tantalum and a first transition metal other than tantalum, wherein a first interface between the first barrier layer and the dielectric layer has a first stress level. A second barrier layer is positioned on the first barrier layer, the second barrier layer including at least one of tantalum and tantalum nitride, wherein a second interface between the second barrier layer and the first barrier layer has a second stress level that is less than the first stress level. The interconnect structure further includes a fill material substantially filling the recess.

Abstract translation: 半导体器件包括限定在介电层中的凹部和限定在凹部中的互连结构。 所述互连结构包括衬在所述凹部中的第一阻挡层，所述第一阻挡层包括钽合金和除了钽之外的第一过渡金属，其中所述第一阻挡层和所述介电层之间的第一界面具有第一应力水平。 第二阻挡层位于第一阻挡层上，第二阻挡层包括钽和氮化钽中的至少一个，其中第二阻挡层和第一阻挡层之间的第二界面具有小于第二阻挡层的第二应力水平 第一压力水平。 互连结构还包括基本上填充凹部的填充材料。

公开(公告)号：US08932934B2

公开(公告)日：2015-01-13

申请号：US13903283

申请日：2013-05-28

Applicant: GlobalFoundries Inc.

Inventor： Moosung M. Chae ,  Errol Todd Ryan ,  Nicholas Vincent Licausi ,  Christian Witt ,  Ailian Zhao ,  Ming He ,  Sean X. Lin ,  Xunyuan Zhang ,  Kunaljeet Tanwar

IPC: H01L21/76 ,  H01L21/768 ,  H01L23/48 ,  H01L21/316 ,  H01L21/02

CPC classification number: H01L21/76831 ,  H01L21/02203 ,  H01L21/3105 ,  H01L21/31695 ,  H01L21/7682 ,  H01L21/76843 ,  H01L2221/1047

Abstract: A process is provided for methods of reducing contamination of the self-forming barrier of an ultra-low k layer during semiconductor fabrication. In one aspect, a method includes: providing a cured ultra-low k film which contains at least one trench, and the pores of the film are filled with a pore-stuffing material; removing exposed pore-stuffing material at the surface of the trench to form exposed pores; and forming a self-forming barrier layer on the surface of the trench.

Abstract translation: 提供了一种用于在半导体制造期间减少超低k层的自形成势垒的污染的方法的方法。 一方面，一种方法包括：提供包含至少一个沟槽的固化的超低k膜，并且用孔填充材料填充膜的孔; 在沟槽的表面去除暴露的孔隙填充材料以形成暴露的孔; 并在沟槽的表面上形成自形成阻挡层。