公开(公告)号：US20110019368A1

公开(公告)日：2011-01-27

申请号：US12507591

申请日：2009-07-22

申请人： Paul Stephen Andry ,  Harm Peter Hofstee ,  George A. Katopis ,  John Ulrich Knickerbocker ,  Robert K. Montoye ,  Chirag S. Patel

发明人： Paul Stephen Andry ,  Harm Peter Hofstee ,  George A. Katopis ,  John Ulrich Knickerbocker ,  Robert K. Montoye ,  Chirag S. Patel

IPC分类号： H05K1/18 ,  C23F1/00

CPC分类号： H01L25/0655 ,  H01L23/147 ,  H01L23/60 ,  H01L25/0652 ,  H01L2224/16225 ,  H01L2924/10253 ,  H01L2924/157 ,  Y02T10/82 ,  H01L2924/00

摘要： A silicon carrier structure for electronic packaging includes a base substrate, a silicon carrier substrate disposed on the base substrate, a memory chip disposed on the silicon carrier substrate, a microprocessor chip disposed on the silicon carrier substrate, an input/output chip disposed on the silicon carrier substrate, and a clocking chip disposed on the silicon carrier substrate.

摘要翻译： 一种用于电子封装的硅载体结构包括基底，设置在基底基板上的硅载体衬底，设置在硅载体衬底上的存储芯片，设置在硅载体衬底上的微处理器芯片，设置在硅衬底上的输入/输出芯片 硅载体衬底和设置在硅载体衬底上的时钟芯片。

公开(公告)号：US20090194864A1

公开(公告)日：2009-08-06

申请号：US12024394

申请日：2008-02-01

申请人： Bing Dang ,  John Ulrich Knickerbocker ,  Cornelia Kang-I Tsang

发明人： Bing Dang ,  John Ulrich Knickerbocker ,  Cornelia Kang-I Tsang

IPC分类号： H01L23/538

CPC分类号： H01L23/3736 ,  H01L23/055 ,  H01L23/42 ,  H01L23/49827 ,  H01L23/5384 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/165 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/29111 ,  H01L2224/32145 ,  H01L2224/73153 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2224/13111 ,  H01L2924/00014 ,  H01L2924/00

摘要： An apparatus for an integrated module. A silicon carrier with through-silicon vias has a plurality of die connected to a top side of the silicon carrier. In addition, a substrate is connected to a bottom side of the silicon carrier. The substrate is coupled to the plurality of die via the through-silicon vias.

摘要翻译： 一种用于集成模块的装置。 具有通硅通孔的硅载体具有连接到硅载体的顶侧的多个管芯。 此外，衬底连接到硅载体的底侧。 衬底通过硅通孔耦合到多个管芯。

公开(公告)号：US07486525B2

公开(公告)日：2009-02-03

申请号：US11499573

申请日：2006-08-04

申请人： John Ulrich Knickerbocker

发明人： John Ulrich Knickerbocker

IPC分类号： H05K7/00

CPC分类号： G01R1/0483 ,  G01R1/0425 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  Y10T29/49144 ,  Y10T29/49224 ,  Y10T29/49819 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2924/00014

摘要： A temporary chip attach carrier for and a method of testing an integrated circuit chip. The carrier includes: a substrate, a first array of interconnects disposed on a bottom surface and a second array of interconnects disposed on a top surface of the substrate, corresponding interconnects of the first and second arrays of interconnects electrically connected by wires in the substrate; an interposer, a first array of pads disposed on a top surface of the interposer and a second array of pads disposed on a bottom surface of the interposer, corresponding pads of the first and second arrays of pads electrically connected by wires in the interposer, and pads of the second array in direct physical and electrical contact with corresponding interconnects of the second set of interconnects; and wherein the interposer includes an interposer substrate of the same material as a substrate of the integrated circuit chip.

摘要翻译： 一种用于测试集成电路芯片的临时芯片连接载体和方法。 载体包括：衬底，布置在底表面上的第一互连阵列和布置在衬底的顶表面上的第二互连阵列，通过衬底中的导线电连接的第一和第二互连阵列的对应互连; 插入器，布置在插入器的顶表面上的第一阵列阵列和布置在插入器的底表面上的第二阵列阵列，通过插入器中的导线电连接的第一和第二阵列阵列的对应焊盘，以及 所述第二阵列的焊盘与所述第二组互连的对应互连件直接物理和电接触; 并且其中所述插入器包括与所述集成电路芯片的基板相同材料的插入器基板。

公开(公告)号：US20080164573A1

公开(公告)日：2008-07-10

申请号：US11620423

申请日：2007-01-05

申请人： Veeraraghaven S. Basker ,  John Michael Cotte ,  Hariklia Deligianni ,  John Ulrich Knickerbocker ,  Keith T. Kwietniak

发明人： Veeraraghaven S. Basker ,  John Michael Cotte ,  Hariklia Deligianni ,  John Ulrich Knickerbocker ,  Keith T. Kwietniak

IPC分类号： H01L21/768 ,  H01L23/522

CPC分类号： H01L23/433 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/055 ,  H01L23/481 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3025 ,  H01L2924/00

摘要： Methods are provided for fabricating silicon carriers with conductive through-vias that allow high-yield manufacture of silicon carrier with, low defect density. In particular, methods are provided which enable fabrication of silicon, carries with via diameters such as 1 to 10 microns in diameter for a vertical thickness of less than 10 micrometers to greater than 300 micrometers, which are capable robust to thermal-mechanical stresses during production to significantly minimize the thermal mechanical movement at the via sidewall interface between the silicon, insulator, liner and conductor materials.

摘要翻译： 提供了用于制造具有导电通孔的硅载体的方法，其允许以低缺陷密度高产量制造硅载体。 特别地，提供了能够制造硅的方法，具有通孔直径，例如直径为1至10微米，垂直厚度小于10微米至大于300微米，这对于生产过程中的热机械应力是坚固的 以显着地最小化硅，绝缘体，衬里和导体材料之间的通孔侧壁界面处的热机械运动。

公开(公告)号：US06376983B1

公开(公告)日：2002-04-23

申请号：US09116403

申请日：1998-07-16

申请人： John Stuart Beeteson ,  John Ulrich Knickerbocker ,  Andrew Ramsay Knox ,  Anthony Cyril Lowe

发明人： John Stuart Beeteson ,  John Ulrich Knickerbocker ,  Andrew Ramsay Knox ,  Anthony Cyril Lowe

IPC分类号： H01J2948

CPC分类号： H01J29/68 ,  H01J3/021 ,  H01J29/028 ,  H01J29/467 ,  H01J2329/00 ,  H01J2329/8625 ,  H01J2329/863

摘要： An electron source comprises at least one cathode means, and at least one extractor grid which is used to extract electrons from the cathode means. The extractor grid is a substantially planar sheet having at least one aperture and also has at least one spacing member for spacing the extractor grid at a constant, predetermined spacing from the cathode. Each of the spacing members are formed by removing material around a substantial portion of the periphery of the aperture and folding the remaining portion of the periphery of the aperture at substantially a right angle to the planar sheet.

摘要翻译： 电子源包括至少一个阴极装置和用于从阴极装置提取电子的至少一个提取器栅格。 提取器格栅是具有至少一个孔的基本上平面的片，并且还具有用于以与阴极恒定的预定间隔隔开提取器栅格的至少一个间隔构件。 每个间隔构件通过除去围绕孔的周边的大部分的材料并且将孔的周边的剩余部分以与基板成直角的角度折叠而形成。

公开(公告)号：US5986395A

公开(公告)日：1999-11-16

申请号：US854285

申请日：1997-05-09

申请人： John Ulrich Knickerbocker ,  Andrew Ramsay Knox ,  Robert Rosenberg

发明人： John Ulrich Knickerbocker ,  Andrew Ramsay Knox ,  Robert Rosenberg

IPC分类号： H01F1/00 ,  H01F7/02 ,  H01F41/16 ,  H01J29/68 ,  H01J29/70 ,  H01J29/74

CPC分类号： H01J29/68 ,  H01F41/16 ,  H01F7/0278

摘要： A metal/ferrite laminate magnet has perforations forming apertures in the magnet. The magnet is formed of outside metal plates surrounding a sandwich of two layers of ferrite material. The outside metal plates allow the perforations to be made in the magnet before sintering of the magnet and maintain the alignment of the holes during sintering. The metal plates also provide the magnet with mechanical robustness and rigidity and prevent cracking occurring between adjacent apertures.

摘要翻译： 金属/铁氧体层叠磁体具有在磁体中形成孔的穿孔。 磁体由围绕两层铁素体材料的夹层的外部金属板形成。 外部金属板允许在磁体烧结之前在磁体中形成穿孔，并且在烧结期间保持孔的对准。 金属板还为磁体提供机械坚固性和刚性，并防止在相邻孔之间发生裂纹。

公开(公告)号：US5891543A

公开(公告)日：1999-04-06

申请号：US703828

申请日：1996-08-27

申请人： Jon Alfred Casey ,  Cynthia Jeane Calli ,  Darren T. Cook ,  David B. Goland ,  John Ulrich Knickerbocker ,  Mark Joseph LaPlante ,  David Clifford Long ,  Daniel Scott Mackin ,  Kathleen Mary McGuire ,  Keith Colin O'Neil ,  Kevin Michael Prettyman ,  Michael Thomas Puchalski ,  Joseph Christopher Saltarelli ,  Candace Anne Sullivan

发明人： Jon Alfred Casey ,  Cynthia Jeane Calli ,  Darren T. Cook ,  David B. Goland ,  John Ulrich Knickerbocker ,  Mark Joseph LaPlante ,  David Clifford Long ,  Daniel Scott Mackin ,  Kathleen Mary McGuire ,  Keith Colin O'Neil ,  Kevin Michael Prettyman ,  Michael Thomas Puchalski ,  Joseph Christopher Saltarelli ,  Candace Anne Sullivan

IPC分类号： H01L21/48 ,  H01L21/683 ,  H05K1/03 ,  H05K3/40 ,  B32B3/02

CPC分类号： H05K3/4061 ,  H01L21/4867 ,  H01L21/6833 ,  H05K1/0306 ,  H05K2203/105 ,  Y10T156/1056 ,  Y10T156/1158 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49139 ,  Y10T428/239 ,  Y10T428/31 ,  Y10T428/31786

摘要： The present invention relates generally to a new apparatus and method for screening using electrostatic adhesion. More particularly, the invention encompasses an apparatus that uses an electrostatic charge during the screening process for a semiconductor substrate. Basically, a backing layer is adhered to a green ceramic sheet using an electrostatic charge, while the green ceramic sheet is processed.

摘要翻译： 本发明一般涉及使用静电粘附进行筛选的新装置和方法。 更具体地，本发明包括在半导体衬底的筛选过程中使用静电电荷的装置。 基本上，使用静电荷将背衬层附着在生坯陶瓷片上，同时处理生坯陶瓷片。

公开(公告)号：US08354737B2

公开(公告)日：2013-01-15

申请号：US12983552

申请日：2011-01-03

申请人： Paul S Andry ,  John M Cotte ,  John Ulrich Knickerbocker ,  Cornelia K Tsang

发明人： Paul S Andry ,  John M Cotte ,  John Ulrich Knickerbocker ,  Cornelia K Tsang

IPC分类号： H01L21/44

CPC分类号： H01L21/76898 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/80 ,  H01L24/94 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/94 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor structure includes: at least one silicon surface wherein the surface can be a substrate, wafer or other device. The structure further includes at least one electronic circuit formed on each side of the at least one surface; and at least one conductive high aspect ratio through silicon via running through the at least one surface. Each through silicon via is fabricated from at least one etch step and includes: at least one thermal oxide dielectric for coating at least some of a sidewall of the through silicon via for a later etch stop in fabrication of the through silicon via.

摘要翻译： 半导体结构包括：至少一个硅表面，其中该表面可以是衬底，晶片或其它器件。 该结构还包括形成在至少一个表面的每一侧上的至少一个电子电路; 以及通过硅穿过所述至少一个表面的至少一个导电高宽比。 每个通过硅通孔由至少一个蚀刻步骤制造，并且包括：至少一个热氧化物电介质，用于涂覆通孔硅通孔的侧壁中的至少一些，用于随后的通孔硅制造中的蚀刻停止。

公开(公告)号：US08213184B2

公开(公告)日：2012-07-03

申请号：US12195515

申请日：2008-08-21

申请人： John Ulrich Knickerbocker

发明人： John Ulrich Knickerbocker

IPC分类号： H05K7/00

CPC分类号： G01R1/0483 ,  G01R1/0425 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  Y10T29/49144 ,  Y10T29/49224 ,  Y10T29/49819 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2924/00014

摘要： A method of testing integrated circuit chips. The method includes: attaching integrated circuit chips to an interposer of a temporary carrier, the carrier comprising: a substrate, a first interconnects on a bottom surface and a second array of interconnects on a top surface of the substrate, corresponding first and second interconnects electrically connected by wires in the substrate; the interposer, first pads on a top surface and a second pads on a bottom surface of the interposer, corresponding first and second pads electrically connected by wires in the interposer, and the second pads in physical and electrical contact with corresponding second interconnects; and the interposer including an interposer substrate comprising a same material as a substrate of the integrated circuit chip; connecting interconnects of the first array of interconnects to a tester; and testing the one or more integrated circuit chips.

摘要翻译： 一种测试集成电路芯片的方法。 该方法包括：将集成电路芯片附接到临时载体的插入器，所述载体包括：衬底，在底表面上的第一互连和在衬底的顶表面上的第二互连阵列，对应的第一和第二互连电 通过基板上的电线连接; 插入器，顶表面上的第一焊盘和内插器的底表面上的第二焊盘，对应的第一和第二焊盘通过插入件中的导线电连接，第二焊盘与对应的第二互连物理和电接触; 并且所述插入器包括包含与所述集成电路芯片的基板相同的材料的插入器基板; 将所述第一互连阵列的互连件连接到测试器; 并测试一个或多个集成电路芯片。

公开(公告)号：US08138015B2

公开(公告)日：2012-03-20

申请号：US13219801

申请日：2011-08-29

申请人： Douglas James Joseph ,  John Ulrich Knickerbocker

发明人： Douglas James Joseph ,  John Ulrich Knickerbocker

IPC分类号： H01L21/00

CPC分类号： H01L23/49833 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00013 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2224/29099

摘要： A structure formation method. The method may include: attaching a substrate, a first interposer, a second interposer, and a first bridge together such that the first interposer is on and electrically connected to the substrate, the second interposer is on and electrically connected to the substrate, the first interposer comprises at least a first transistor, and the second interposer comprises at least a second transistor. The method may alternatively include: disposing both a first and second interposer on a substrate, wherein the first and second interposer are each electrically connected to the substrate; and electrically connecting a first bridge to the first and second interposers, wherein (i) the first bridge is in direct physical contact with the substrate or (ii) a bottom surface of the first bridge is within the substrate and below a top surface of the substrate.

摘要翻译： 一种结构形成方法。 该方法可以包括：将基板，第一插入件，第二插入件和第一桥接器连接在一起，使得第一插入件在基板上并电连接到第二插入器，第二插入器在基板上并电连接到第一基板 至少包括第一晶体管，并且第二插入器至少包括第二晶体管。 该方法可以可替代地包括：将第一和第二插入件布置在衬底上，其中第一和第二插入器各自电连接到衬底; 以及将第一桥接电连接到所述第一和第二插入件，其中（i）所述第一桥与所述衬底直接物理接触，或（ii）所述第一桥的底表面在所述衬底内并且位于所述衬底的顶表面之下 基质。