公开(公告)号：US5891543A

公开(公告)日：1999-04-06

申请号：US703828

申请日：1996-08-27

申请人： Jon Alfred Casey ,  Cynthia Jeane Calli ,  Darren T. Cook ,  David B. Goland ,  John Ulrich Knickerbocker ,  Mark Joseph LaPlante ,  David Clifford Long ,  Daniel Scott Mackin ,  Kathleen Mary McGuire ,  Keith Colin O'Neil ,  Kevin Michael Prettyman ,  Michael Thomas Puchalski ,  Joseph Christopher Saltarelli ,  Candace Anne Sullivan

发明人： Jon Alfred Casey ,  Cynthia Jeane Calli ,  Darren T. Cook ,  David B. Goland ,  John Ulrich Knickerbocker ,  Mark Joseph LaPlante ,  David Clifford Long ,  Daniel Scott Mackin ,  Kathleen Mary McGuire ,  Keith Colin O'Neil ,  Kevin Michael Prettyman ,  Michael Thomas Puchalski ,  Joseph Christopher Saltarelli ,  Candace Anne Sullivan

IPC分类号： H01L21/48 ,  H01L21/683 ,  H05K1/03 ,  H05K3/40 ,  B32B3/02

CPC分类号： H05K3/4061 ,  H01L21/4867 ,  H01L21/6833 ,  H05K1/0306 ,  H05K2203/105 ,  Y10T156/1056 ,  Y10T156/1158 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49139 ,  Y10T428/239 ,  Y10T428/31 ,  Y10T428/31786

摘要： The present invention relates generally to a new apparatus and method for screening using electrostatic adhesion. More particularly, the invention encompasses an apparatus that uses an electrostatic charge during the screening process for a semiconductor substrate. Basically, a backing layer is adhered to a green ceramic sheet using an electrostatic charge, while the green ceramic sheet is processed.

摘要翻译： 本发明一般涉及使用静电粘附进行筛选的新装置和方法。 更具体地，本发明包括在半导体衬底的筛选过程中使用静电电荷的装置。 基本上，使用静电荷将背衬层附着在生坯陶瓷片上，同时处理生坯陶瓷片。

公开(公告)号：US5759669A

公开(公告)日：1998-06-02

申请号：US577179

申请日：1995-12-22

申请人： Jon Alfred Casey ,  Cynthia Jeane Calli ,  Darren T. Cook ,  David B. Goland ,  John Ulrich Knickerbocker ,  Mark Joseph LaPlante ,  David Clifford Long ,  Daniel Scott Mackin ,  Kathleen Mary McGuire ,  Keith Colin O'Neil ,  Kevin Michael Prettyman ,  Michael Thomas Puchalski ,  Joseph Christopher Saltarelli ,  Candace Anne Sullivan

发明人： Jon Alfred Casey ,  Cynthia Jeane Calli ,  Darren T. Cook ,  David B. Goland ,  John Ulrich Knickerbocker ,  Mark Joseph LaPlante ,  David Clifford Long ,  Daniel Scott Mackin ,  Kathleen Mary McGuire ,  Keith Colin O'Neil ,  Kevin Michael Prettyman ,  Michael Thomas Puchalski ,  Joseph Christopher Saltarelli ,  Candace Anne Sullivan

IPC分类号： B32B3/08 ,  B32B3/26 ,  B32B15/02 ,  H05K1/03 ,  H05K3/40 ,  B29C37/00 ,  B32B3/24

CPC分类号： B32B15/02 ,  B32B3/08 ,  B32B3/26 ,  H05K3/4061 ,  H05K1/0306 ,  H05K2203/0156 ,  H05K2203/082 ,  Y10S428/901 ,  Y10T29/49163 ,  Y10T428/24273 ,  Y10T428/24322 ,  Y10T428/24331 ,  Y10T428/24339 ,  Y10T428/24802

摘要： The present invention relates generally to a new apparatus and method for screening using porous backing material. More particularly, the invention encompasses an apparatus that uses a porous backing material which is adhered to a green sheet during the screening process. Basically, a backing layer having a very high porosity is adhered to a green sheet, while the green sheet is screened. During the drying process of the green sheet some of the screening fluids are absorbed by the porous backing layer, which allows the screened vias of the green sheet to have a smooth surface.

摘要翻译： 本发明一般涉及使用多孔背衬材料进行筛选的新装置和方法。 更具体地说，本发明包括使用在筛选过程中粘附到生片上的多孔背衬材料的装置。 基本上，具有非常高的孔隙率的背衬层粘附到生片上，同时筛分生片。 在生片的干燥过程中，一些筛选液被多孔背衬层吸收，这允许生片的筛选通孔具有光滑的表面。

公开(公告)号：US20120326321A1

公开(公告)日：2012-12-27

申请号：US13600716

申请日：2012-08-31

申请人： Alain Caron ,  John Ulrich Knickerbocker

发明人： Alain Caron ,  John Ulrich Knickerbocker

IPC分类号： H01L23/48

CPC分类号： H01L23/5385 ,  H01L21/486 ,  H01L23/5384 ,  H01L23/60 ,  H01L24/16 ,  H01L25/0652 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2224/48

摘要： Techniques for modular chip fabrication are provided. In one aspect, a modular chip structure is provided. The modular chip structure comprises a substrate; a carrier platform attached to the substrate, the carrier platform comprising a plurality of conductive vias extending through the carrier platform; and a wiring layer on the carrier platform in contact with one or more of the conductive vias, wherein the wiring layer comprises one or more wiring levels and is configured to divide the carrier platform into a plurality of voltage islands; and chips, chip macros or at least one chip in combination with at least one chip macro assembled on the carrier platform.

摘要翻译： 提供了模块化芯片制造技术。 一方面，提供了一种模块化芯片结构。 模块化芯片结构包括基板; 载体平台，其附接到所述基底，所述载体平台包括延伸穿过所述载体平台的多个导电通孔; 以及载体平台上的一个或多个导电通孔接触的布线层，其中所述布线层包括一个或多个布线层，并且被配置为将所述载体平台划分成多个电压岛; 芯片，芯片宏或至少一个芯片组合在载体平台上组装的至少一个芯片宏。

公开(公告)号：US20120301977A1

公开(公告)日：2012-11-29

申请号：US13569872

申请日：2012-08-08

申请人： Paul Stephen Andry ,  Harm Peter Hofstee ,  George A. Katopis ,  John Ulrich Knickerbocker ,  Robert K. Montoye ,  Chirag S. Patel

发明人： Paul Stephen Andry ,  Harm Peter Hofstee ,  George A. Katopis ,  John Ulrich Knickerbocker ,  Robert K. Montoye ,  Chirag S. Patel

IPC分类号： H01L21/66 ,  G06F17/50

CPC分类号： H01L25/0655 ,  H01L23/147 ,  H01L23/60 ,  H01L25/0652 ,  H01L2224/16225 ,  H01L2924/10253 ,  H01L2924/157 ,  H01L2924/00

摘要： A silicon carrier structure for electronic packaging includes a base substrate, a silicon carrier substrate disposed on the base substrate, a memory chip disposed on the silicon carrier substrate, a microprocessor chip disposed on the silicon carrier substrate, an input/output chip disposed on the silicon carrier substrate, and a clocking chip disposed on the silicon carrier substrate.

摘要翻译： 一种用于电子封装的硅载体结构包括基底，设置在基底基板上的硅载体衬底，设置在硅载体衬底上的存储芯片，设置在硅载体衬底上的微处理器芯片，设置在硅衬底上的输入/输出芯片 硅载体衬底和设置在硅载体衬底上的时钟芯片。

公开(公告)号：US07750459B2

公开(公告)日：2010-07-06

申请号：US12024394

申请日：2008-02-01

申请人： Bing Dang ,  John Ulrich Knickerbocker ,  Cornelia Kang-I Tsang

发明人： Bing Dang ,  John Ulrich Knickerbocker ,  Cornelia Kang-I Tsang

IPC分类号： H01L23/538

CPC分类号： H01L23/3736 ,  H01L23/055 ,  H01L23/42 ,  H01L23/49827 ,  H01L23/5384 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/165 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/29111 ,  H01L2224/32145 ,  H01L2224/73153 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2224/13111 ,  H01L2924/00014 ,  H01L2924/00

摘要： An apparatus for an integrated module. A silicon carrier with through-silicon vias has a plurality of die connected to a top side of the silicon carrier. In addition, a substrate is connected to a bottom side of the silicon carrier. The substrate is coupled to the plurality of die via the through-silicon vias.

摘要翻译： 一种用于集成模块的装置。 具有通硅通孔的硅载体具有连接到硅载体顶侧的多个管芯。 此外，衬底连接到硅载体的底侧。 衬底通过硅通孔耦合到多个管芯。

公开(公告)号：US20090267238A1

公开(公告)日：2009-10-29

申请号：US12110579

申请日：2008-04-28

申请人： Douglas James Joseph ,  John Ulrich Knickerbocker

发明人： Douglas James Joseph ,  John Ulrich Knickerbocker

IPC分类号： H01L23/538 ,  H01L21/60

CPC分类号： H01L23/49833 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00013 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2224/29099

摘要： A structure and a method for forming the same. The structure includes a substrate, a first interposer on the substrate, a second interposer on the substrate, and a first bridge. The first and second interposers are electrically connected to the substrate. The first bridge is electrically connected to the first and second interposers.

摘要翻译： 一种结构及其形成方法。 该结构包括衬底，衬底上的第一插入件，衬底上的第二插入件和第一桥。 第一和第二插入件电连接到基板。 第一桥电连接到第一和第二插入件。

公开(公告)号：US06528145B1

公开(公告)日：2003-03-04

申请号：US09606359

申请日：2000-06-29

申请人： Daniel George Berger ,  Shaji Farooq ,  Lester Wynn Herron ,  James N. Humenik ,  John Ulrich Knickerbocker ,  Robert William Pasco ,  Charles H. Perry ,  Krishna G. Sachdev

发明人： Daniel George Berger ,  Shaji Farooq ,  Lester Wynn Herron ,  James N. Humenik ,  John Ulrich Knickerbocker ,  Robert William Pasco ,  Charles H. Perry ,  Krishna G. Sachdev

IPC分类号： G02B600

CPC分类号： H05K1/0373 ,  H01L21/4857 ,  H01L23/49894 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K3/4611 ,  H05K2201/0129 ,  H05K2201/0141 ,  H05K2201/015 ,  H05K2201/0154 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/068 ,  Y10S428/901 ,  Y10T428/24273 ,  Y10T428/24479 ,  Y10T428/24917 ,  Y10T428/24942 ,  Y10T428/249955 ,  Y10T428/249956 ,  Y10T428/251 ,  Y10T428/254 ,  Y10T428/259 ,  H01L2924/00

摘要： A composite electronic and/or optical substrate including polymeric and ceramic material wherein the composite substrate has a dielectric constant less than 4 and a coefficient of thermal expansion of 8 to 14 ppm/°C. at 100° C. The composite substrate may be either ceramic-filled polymeric material or polymer-filled ceramic material.

摘要翻译： 包括聚合物和陶瓷材料的复合电子和/或光学基底，其中复合基底具有小于4的介电常数和8-14ppm /℃的热膨胀系数。 在100℃下。复合衬底可以是陶瓷填充的聚合材料或聚合物填充的陶瓷材料。

公开(公告)号：US08117982B2

公开(公告)日：2012-02-21

申请号：US12544345

申请日：2009-08-20

申请人： Peter A. Gruber ,  John Ulrich Knickerbocker

发明人： Peter A. Gruber ,  John Ulrich Knickerbocker

IPC分类号： B05B15/04 ,  B05C11/11 ,  B23K35/14 ,  B23K31/00 ,  B23K31/02 ,  B23K35/12

CPC分类号： H05K3/3457 ,  H01L21/288 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/11009 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/1319 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H05K2203/0113 ,  H05K2203/0557 ,  H01L2924/00

摘要： A method and apparatus for the formation of coplanar electrical interconnectors. Solder material is deposited onto a wafer, substrate, or other component of an electrical package using a complaint mold such that the terminal ends of the solder material being deposited, i.e., the ends opposite to those forming an attachment to the wafer, substrate, or other component of an electrical package are coplanar with one another. A complaint mold is used having one or more conduits for receiving solder material and having a compliant side and a planar side. The compliant side of the mold is positioned adjacent to the wafer, substrate, or other component of an electrical package allowing solder material to be deposited onto the surface thereof such that the planar side of the compliant mold provides coplanar interconnectors. An Injection Molded Solder (IMS) head can be used as the means for filling the conduits of the compliant mold of the present invention.

摘要翻译： 用于形成共面电连接器的方法和装置。 使用投诉模具将焊料沉积到电气封装的晶片，基板或其他部件上，使得焊料材料的末端被沉积，即与形成与晶片，基板或附件形成连接的端部相对的端部 电气封装的其他部件彼此共面。 使用投诉模具具有一个或多个用于接收焊料材料并具有柔性侧面和平面侧的导管。 模具的柔性侧被定位成与电气封装的晶片，衬底或其它部件相邻，允许将焊料材料沉积到其表面上，使得柔性模具的平面侧提供共面的互连器件。 可以使用注射成型焊料（IMS）头作为填充本​​发明的柔性模具的导管的装置。

公开(公告)号：US20090111215A1

公开(公告)日：2009-04-30

申请号：US11929612

申请日：2007-10-30

申请人： Alain Caron ,  John Ulrich Knickerbocker

发明人： Alain Caron ,  John Ulrich Knickerbocker

IPC分类号： H01L21/50

CPC分类号： H01L25/0652 ,  H01L23/49827 ,  H01L23/60 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/8185 ,  H01L2224/81895 ,  H01L2224/831 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2224/48

摘要： Modular chip integration and operation techniques are provided. In one aspect, a method of integrating chips, chip macros or at least one chip in combination with at least one chip macro is provided. The method comprises the following steps. The chips, chip macros or at least one chip in combination with at least one chip macro are assembled on a single carrier platform. One or more signal inputs and outputs are provided to each of the chips, chip macros or at least one chip in combination with at least one chip macro. One or more power and ground inputs and outputs are provided to each of the chips, chip macros or at least one chip in combination with at least one chip macro. The power and ground inputs and outputs to one or more of the chips, chip macros or at least one chip in combination with at least one chip macro are segmented from the power and ground inputs and outputs to at least one other of the chips, chip macros or at least one chip in combination with at least one chip macro so as to form a plurality of voltage islands.

摘要翻译： 提供了模块化芯片集成和操作技术。 一方面，提供将芯片，芯片宏或至少一个芯片与至少一个芯片宏组合的方法。 该方法包括以下步骤。 将芯片，芯片宏或至少一个与至少一个芯片宏组合的芯片组装在单个载体平台上。 每个芯片，芯片宏或至少一个芯片与至少一个芯片宏组合提供一个或多个信号输入和输出。 一个或多个电源和接地输入和输出被提供给每个芯片，芯片宏或至少一个芯片与至少一个芯片宏组合。 电源和接地输入和输出到一个或多个芯片，芯片宏或至少一个芯片与至少一个芯片宏的组合被分割成电源和地面输入并输出到至少另一个芯片，芯片 宏或至少一个芯片与至少一个芯片宏组合，以便形成多个电压岛。

公开(公告)号：US07518229B2

公开(公告)日：2009-04-14

申请号：US11498689

申请日：2006-08-03

申请人： John Michael Cotte ,  Brian Paul Gaucher ,  Janusz Grzyb ,  Nils Deneke Hoivik ,  Christopher Vincent Jahnes ,  John Ulrich Knickerbocker ,  Duixian Liu ,  John Harold Magerlein ,  Chirag Suryakant Patel ,  Ullrich R. Pfeiffer ,  Cornelia Kang-I Tsang

发明人： John Michael Cotte ,  Brian Paul Gaucher ,  Janusz Grzyb ,  Nils Deneke Hoivik ,  Christopher Vincent Jahnes ,  John Ulrich Knickerbocker ,  Duixian Liu ,  John Harold Magerlein ,  Chirag Suryakant Patel ,  Ullrich R. Pfeiffer ,  Cornelia Kang-I Tsang

IPC分类号： H01L23/04

CPC分类号： H01L25/165 ,  H01L23/66 ,  H01L24/24 ,  H01L24/82 ,  H01L25/162 ,  H01L2223/6677 ,  H01L2224/16225 ,  H01L2224/24137 ,  H01L2224/24227 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01Q1/2283 ,  H01L2924/00 ,  H01L2224/0401

摘要： An apparatus is described incorporating an interposer having a cavity for a portion of an antenna structure, having conductor through vias, a top Si part having interconnection wiring and having pads for electrically mounting an integrated circuit chip thereon, wherein the top Si part mates with the interposer electrically and mechanically. The interposer and top Si part may be scaled to provide an array of functional units. The invention overcomes the problem of combining a high efficient antenna with integrated circuit chips in a Si package with signal frequencies from 1 to 100 GHz and the problem of shielding components proximate to the antenna and reduces strain arising from mismatching of TCEs.

摘要翻译： 描述了一种装置，其具有用于天线结构的一部分的空腔的插入件，具有导体穿过通孔，顶部Si部分具有互连布线并具有用于在其上电气安装集成电路芯片的焊盘，其中顶部Si部分与 内插器电气和机械。 插入器和顶部Si部分可以被缩放以提供功能单元的阵列。 本发明克服了将高效天线与Si封装中的集成电路芯片组合在一起的信号频率为1至100GHz的问题，以及屏蔽靠近天线的组件的问题，并减少了由于TCE失配引起的应变。