公开(公告)号：US5793099A

公开(公告)日：1998-08-11

申请号：US646031

申请日：1996-05-07

申请人： Gen Murakami ,  Kunihiro Tsubosaki ,  Masahiro Ichitani ,  Kunihiko Nishi ,  Ichiro Anjoh ,  Asao Nishimura ,  Makoto Kitano ,  Akihiro Yaguchi ,  Sueo Kawai ,  Masatsugu Ogata ,  Syuuji Eguchi ,  Hiroyoshi Kokaku ,  Masanori Segawa ,  Hiroshi Hozoji ,  Takashi Yokoyama ,  Noriyuki Kinjo ,  Aizo Kaneda ,  Junichi Saeki ,  Shozo Nakamura ,  Akio Hasebe ,  Hiroshi Kikuchi ,  Isamu Yoshida ,  Takashi Yamazaki ,  Kazuyoshi Oshima ,  Tetsurou Matsumoto

发明人： Gen Murakami ,  Kunihiro Tsubosaki ,  Masahiro Ichitani ,  Kunihiko Nishi ,  Ichiro Anjoh ,  Asao Nishimura ,  Makoto Kitano ,  Akihiro Yaguchi ,  Sueo Kawai ,  Masatsugu Ogata ,  Syuuji Eguchi ,  Hiroyoshi Kokaku ,  Masanori Segawa ,  Hiroshi Hozoji ,  Takashi Yokoyama ,  Noriyuki Kinjo ,  Aizo Kaneda ,  Junichi Saeki ,  Shozo Nakamura ,  Akio Hasebe ,  Hiroshi Kikuchi ,  Isamu Yoshida ,  Takashi Yamazaki ,  Kazuyoshi Oshima ,  Tetsurou Matsumoto

IPC分类号： H01L21/52 ,  H01L23/31 ,  H01L23/495 ,  H01L23/50 ,  H01L25/10 ,  H01L29/06 ,  H05K1/14 ,  H05K1/18 ,  H05K3/34

CPC分类号： H01L23/3107 ,  H01L23/4951 ,  H01L23/49555 ,  H01L23/49558 ,  H01L23/49568 ,  H01L23/49586 ,  H01L24/32 ,  H01L24/49 ,  H01L25/105 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/16245 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/48799 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85205 ,  H01L2224/8592 ,  H01L2224/92147 ,  H01L2225/1005 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01043 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01092 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/144 ,  H05K1/181 ,  H05K3/3421

摘要： As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

公开(公告)号：US5110515A

公开(公告)日：1992-05-05

申请号：US353256

申请日：1989-05-16

申请人： Shozo Nakamura ,  Aizo Kaneda ,  Shigeharu Tsunoda ,  Akio Hasebe ,  Masao Mitani

发明人： Shozo Nakamura ,  Aizo Kaneda ,  Shigeharu Tsunoda ,  Akio Hasebe ,  Masao Mitani

IPC分类号： B29C45/02 ,  B29C45/14 ,  B29C45/72 ,  B29L31/34 ,  H01L21/56

CPC分类号： B29C45/14655 ,  B29C45/1468 ,  B29C45/7207 ,  H01L21/565 ,  H01L2924/0002

摘要： A method for manufacturing plastic package for semiconductor according to the present invention comprises the steps of: forming a mold product of plastic package for semiconductor, which contains therein a semiconductor chip, by molding resin by means of a transfer press; heating the mold product to postcure it during transportation from the transfer press to a heating chamber while the mold product is kept by heaters at a temperature higher than a glass transition temperature of the resin for a predetermined period of time; and further heating the mold product in the heating chamber while the mold product is kept at a temperature substantially equal to the glass transition temperature of the resin for another predetermined period of time.

摘要翻译： 根据本发明的用于制造半导体用塑料封装件的方法包括以下步骤：通过转印压模成型树脂来形成其中包含半导体芯片的用于半导体的塑料封装的模具产品; 在模具产品通过加热器在高于树脂的玻璃化转变温度的温度下保持预定时间段时，加热模具产品以在从转印压机传送到加热室的过程中将其后固化; 并且在模具产品保持在基本上等于树脂的玻璃化转变温度的温度另外预定时间段的情况下，进一步加热加热室中的模具产品。

公开(公告)号：US5068712A

公开(公告)日：1991-11-26

申请号：US409332

申请日：1989-09-19

申请人： Gen Murakami ,  Kunihiro Tsubosaki ,  Masahiro Ichitani ,  Kunihiko Nishi ,  Ichiro Anjo ,  Asao Nishimura ,  Makoto Kitano ,  Akihiro Yaguchi ,  Sueo Kawai ,  Masatsugu Ogata ,  Syuuji Eguchi ,  Hiroyoshi Kokaku ,  Masanori Segawa ,  Hiroshi Hozoji ,  Takashi Yokoyama ,  Noriyuki Kinjo ,  Aizo Kaneda ,  Junichi Saeki ,  Shozo Nakamura ,  Akio Hasebe ,  Hiroshi Kikuchi ,  Isamu Yoshida ,  Takashi Yamazaki ,  Kazuyoshi Oshima ,  Tetsuro Matsumoto

发明人： Gen Murakami ,  Kunihiro Tsubosaki ,  Masahiro Ichitani ,  Kunihiko Nishi ,  Ichiro Anjo ,  Asao Nishimura ,  Makoto Kitano ,  Akihiro Yaguchi ,  Sueo Kawai ,  Masatsugu Ogata ,  Syuuji Eguchi ,  Hiroyoshi Kokaku ,  Masanori Segawa ,  Hiroshi Hozoji ,  Takashi Yokoyama ,  Noriyuki Kinjo ,  Aizo Kaneda ,  Junichi Saeki ,  Shozo Nakamura ,  Akio Hasebe ,  Hiroshi Kikuchi ,  Isamu Yoshida ,  Takashi Yamazaki ,  Kazuyoshi Oshima ,  Tetsuro Matsumoto

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/31 ,  H01L23/495 ,  H01L25/10 ,  H01L29/06 ,  H05K1/14 ,  H05K1/18 ,  H05K3/34

CPC分类号： H01L24/32 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49555 ,  H01L23/49558 ,  H01L23/49568 ,  H01L23/49586 ,  H01L24/05 ,  H01L24/06 ,  H01L25/105 ,  H01L29/0657 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/06136 ,  H01L2224/16 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/48799 ,  H01L2224/73215 ,  H01L2224/85205 ,  H01L2224/8592 ,  H01L2225/1005 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01043 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01092 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/144 ,  H05K1/181 ,  H05K3/3421 ,  Y10T29/49121

摘要： As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

摘要翻译： 由于半导体芯片尺寸大，高集成度和加速度，所以难以将半导体芯片与包装中的引线组合在一起。 鉴于这种困难，已经采用称为半导体和引线堆叠和封装的称为“片上引线”或“引线芯片”结构的封装结构。 在该结构的封装中，根据本发明，内引线和半导体芯片的前端部之间的间隙比除引导端部和半导体芯片之外的内引线部分之间的间隙宽，从而减小 杂散容量，提高信号传输速率和减少电气噪声。

公开(公告)号：US20110175634A1

公开(公告)日：2011-07-21

申请号：US13075666

申请日：2011-03-30

申请人： Masayoshi Okamoto ,  Yoshiaki Hasegawa ,  Yasuhiro Motoyama ,  Hideyuki Matsumoto ,  Shingo Yorisaki ,  Akio Hasebe ,  Ryuji Shibata ,  Yasunori Narizuka ,  Akira Yabushita ,  Toshiyuki Majima

发明人： Masayoshi Okamoto ,  Yoshiaki Hasegawa ,  Yasuhiro Motoyama ,  Hideyuki Matsumoto ,  Shingo Yorisaki ,  Akio Hasebe ,  Ryuji Shibata ,  Yasunori Narizuka ,  Akira Yabushita ,  Toshiyuki Majima

IPC分类号： G01R31/3187 ,  G01R31/20

CPC分类号： H01L22/14 ,  G01R1/06711 ,  G01R1/06744 ,  G01R1/07307 ,  G01R3/00 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/45144 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/49171 ,  H01L2924/014 ,  H01L2924/3011 ,  H01L2924/00

摘要： To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between interconnects and the metal films, and the interconnects are electrically connected to the metal films. A plane pattern of one of the metal films equipped with one probe and through-hole is obtained by turning a plane pattern of the other metal film equipped with the other probe and through-hole through a predetermined angle.

公开(公告)号：US20100304510A1

公开(公告)日：2010-12-02

申请号：US12853360

申请日：2010-08-10

申请人： Masayoshi OKAMOTO ,  Yoshiaki Hasegawa ,  Yasuhiro Motoyama ,  Hideyuki Matsumoto ,  Shingo Yorisaki ,  Akio Hasebe ,  Ryuji Shibata ,  Yasunori Narizuka ,  Akira Yabushita ,  Toshiyuki Majima

发明人： Masayoshi OKAMOTO ,  Yoshiaki Hasegawa ,  Yasuhiro Motoyama ,  Hideyuki Matsumoto ,  Shingo Yorisaki ,  Akio Hasebe ,  Ryuji Shibata ,  Yasunori Narizuka ,  Akira Yabushita ,  Toshiyuki Majima

IPC分类号： H01L21/66

CPC分类号： H01L22/14 ,  G01R1/06711 ,  G01R1/06744 ,  G01R1/07307 ,  G01R3/00 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/45144 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/49171 ,  H01L2924/014 ,  H01L2924/3011 ,  H01L2924/00

摘要： To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between interconnects and the metal films, and the interconnects are electrically connected to the metal films. A plane pattern of one of the metal films equipped with one probe and through-hole is obtained by turning a plane pattern of the other metal film equipped with the other probe and through-hole through a predetermined angle.

摘要翻译： 为了允许具有金字塔或梯形金字塔形式的窄间距探针设置的测试焊盘的半导体集成电路器件进行电气测试，是由依次层叠铑膜和镍膜而形成的金属膜形成的。 在互连和金属膜之间的聚酰亚胺膜中形成通孔，并且互连电连接到金属膜。 通过将配备有另一个探针和通孔的另一金属膜的平面图案转过预定角度，获得装配有一个探针和通孔的金属膜之一的平面图案。

公开(公告)号：US20100279502A1

公开(公告)日：2010-11-04

申请号：US12836580

申请日：2010-07-15

申请人： Akio Hasebe ,  Yasuhiro Motoyama ,  Yasunori Narizuka ,  Seigo Nakamura ,  Kenji Kawakami

发明人： Akio Hasebe ,  Yasuhiro Motoyama ,  Yasunori Narizuka ,  Seigo Nakamura ,  Kenji Kawakami

IPC分类号： H01L21/768

CPC分类号： G01R3/00 ,  G01R1/07342

摘要： A probe having a sufficient height is manufactured by selectively depositing, over the main surface of a wafer, a copper film in a region in which a metal film is to be formed and a region which will be outside an adhesion ring when a probe card is fabricated; forming the metal film, polyimide film, interconnect, another polyimide film, another interconnect and a further polyimide film; and then removing the wafer and copper film. According to the present invention, when probe testing is performed using a prober (thin film probe) having the probe formed in the above-described manner while utilizing the manufacturing technology of semiconductor integrated circuit devices, it is possible to prevent breakage of the prober and a wafer to be tested.

摘要翻译： 通过选择性地在晶片的主表面上沉积在要形成金属膜的区域中的铜膜和当探针卡是在粘合环外部时将在粘合环外部的区域，制造具有足够高度的探针 制造的 形成金属膜，聚酰亚胺膜，互连，另一聚酰亚胺膜，另一互连和另外的聚酰亚胺膜; 然后取出晶片和铜膜。 根据本发明，在利用半导体集成电路器件的制造技术的情况下，使用具有以上述方式形成的探针的探测器（薄膜探针）进行探针测试时，可以防止探测器的破损， 待测试的晶圆。

公开(公告)号：US20090130785A1

公开(公告)日：2009-05-21

申请号：US11719112

申请日：2004-11-18

申请人： Hideyuki Matsumoto ,  Shingo Yorisaki ,  Akio Hasebe ,  Yasuhiro Motoyama ,  Masayoshi Okamoto ,  Yasunori Narizuka

发明人： Hideyuki Matsumoto ,  Shingo Yorisaki ,  Akio Hasebe ,  Yasuhiro Motoyama ,  Masayoshi Okamoto ,  Yasunori Narizuka

IPC分类号： H01L21/66 ,  G01R31/26

CPC分类号： G01R1/0735 ,  G01R3/00

摘要： As the thickness of the card holder for preventing warping of a multilayered wiring substrate 1 is increased, there occurs a problem that a thin film sheet 2 is buried in a card holder and secure contact between probes 7 and test pads cannot be realized. For its prevention, the thin film sheet 2 and a bonding ring 6 are bonded in a state where a tensile force is applied only to the central region IA of the thin film sheet 2, and a tensile force is not applied to an outer peripheral region OA. Then, the height of the bonding ring 6 defining the height up to the probe surface of the thin film sheet 2 is increased, thereby increasing the height up to the probe surface of the thin film sheet 2.

摘要翻译： 随着用于防止多层布线基板1翘曲的卡夹的厚度增加，存在薄膜片2被埋在卡夹中并且不能实现探针7和测试垫之间的牢固接触的​​问题。 为了防止，薄膜片2和接合环6在仅向薄膜片2的中心区域IA施加张力的状态下接合，并且拉伸力不施加到外围区域 OA。 然后，限定高达薄膜片2的探针表面的高度的接合环6的高度增加，从而增加高达薄膜片2的探针表面的高度。

公开(公告)号：US07534629B2

公开(公告)日：2009-05-19

申请号：US11448071

申请日：2006-06-07

申请人： Teruo Shoji ,  Akio Hasebe ,  Yoshinori Deguchi ,  Motoji Murakami ,  Masayoshi Okamoto ,  Yasunori Narizuka ,  Susumu Kasukabe

发明人： Teruo Shoji ,  Akio Hasebe ,  Yoshinori Deguchi ,  Motoji Murakami ,  Masayoshi Okamoto ,  Yasunori Narizuka ,  Susumu Kasukabe

IPC分类号： H01L21/66

CPC分类号： G01R1/0735

摘要： By using a membrane probe formed by using a manufacturing technique for semiconductor integrated circuit devices, the yield of probing collectively performed on a plurality of chips is to be enhanced. A probe card is formed by using a plurality of pushers, each pusher being formed of a POGO pin insulator, POGO pins, an FPC connector, a membrane probe HMS, an impact easing sheet, an impact easing plate, a chip condenser YRS and so on, wherein one or two POGO pins press a plurality of metal films arranged like islands. One or more cuts are made into what matches the chip to be tested in the area of the membrane probe in a direction substantially parallel to the extending direction of wiring electrically connected to probes formed in the membrane probe.

摘要翻译： 通过使用通过使用半导体集成电路器件的制造技术形成的膜探针，将提高在多个芯片上共同执行的探测的产量。 通过使用多个推动器形成探针卡，每个推动器由POGO针绝缘体，POGO针，FPC连接器，膜探针HMS，冲击缓冲片，冲击缓冲板，芯片冷凝器YRS等形成 其中一个或两个POGO销按压布置成岛状的多个金属膜。 将一个或多个切口制成与膜探针区域中基本上平行于电连接到形成在膜探针中的探针的布线的延伸方向的方向匹配的待测芯片。

公开(公告)号：US07517707B2

公开(公告)日：2009-04-14

申请号：US11783778

申请日：2007-04-12

申请人： Masayoshi Okamoto ,  Hideyuki Matsumoto ,  Shingo Yorisaki ,  Akio Hasebe ,  Yasuhiro Motoyama ,  Akira Shimase

发明人： Masayoshi Okamoto ,  Hideyuki Matsumoto ,  Shingo Yorisaki ,  Akio Hasebe ,  Yasuhiro Motoyama ,  Akira Shimase

IPC分类号： H01L31/26

CPC分类号： G01R3/00 ,  G01R1/07307

摘要： Electrical testing is to be performed on a semiconductor integrated circuit device which the test pads formed. To facilitate such testing, the method of manufacture of the semiconductor integrated circuit device employs a probe card which has two or more contact terminals which can contact two or more electrodes. This probe card includes, in opposition to a wiring substrate of the semiconductor integrated circuit device in which a first wiring is formed, a first sheet having two or more contact terminals to contact the two or more electrodes; a second wiring electrically connected to the two or more contact terminals and the first wiring; and first dummy wirings which are near the region of formation of the two or more contact terminals, are arranged to a non-forming region of the second wiring, and do not participate in signal transfer.

摘要翻译： 电测试将在形成测试焊盘的半导体集成电路器件上进行。 为了便于这种测试，半导体集成电路器件的制造方法采用具有两个或更多个能够接触两个或更多个电极的接触端子的探针卡。 该探针卡与形成有第一布线的半导体集成电路器件的布线基板相对应，具有接触两个以上的电极的两个以上的接触端子的第一片; 电连接到所述两个或更多个接触端子和所述第一布线的第二布线; 并且在两个或多个接触端子的形成区域附近的第一虚拟布线被布置到第二布线的非形成区域，并且不参与信号传递。

公开(公告)号：US20070190671A1

公开(公告)日：2007-08-16

申请号：US11783778

申请日：2007-04-12

申请人： Masayoshi Okamoto ,  Hideyuki Matsumoto ,  Shingo Yorisaki ,  Akio Hasebe ,  Yasuhiro Motoyama ,  Akira Shimase

发明人： Masayoshi Okamoto ,  Hideyuki Matsumoto ,  Shingo Yorisaki ,  Akio Hasebe ,  Yasuhiro Motoyama ,  Akira Shimase

IPC分类号： H01L21/66

CPC分类号： G01R3/00 ,  G01R1/07307

摘要： Electrical testing is to be performed on a semiconductor integrated circuit device which the test pads formed. To facilitate such testing, the method of manufacture of the semiconductor integrated circuit device employs a probe card which has two or more contact terminals which can contact two or more electrodes. This probe card includes, in opposition to a wiring substrate of the semiconductor integrated circuit device in which a first wiring is formed, a first sheet having two or more contact terminals to contact the two or more electrodes; a second wiring electrically connected to the two or more contact terminals and the first wiring; and first dummy wirings which are near the region of formation of the two or more contact terminals, are arranged to a non-forming region of the second wiring, and do not participate in signal transfer.

摘要翻译： 电测试将在形成测试焊盘的半导体集成电路器件上进行。 为了便于这种测试，半导体集成电路器件的制造方法采用具有两个或更多个能够接触两个或更多个电极的接触端子的探针卡。 该探针卡与形成有第一布线的半导体集成电路器件的布线基板相对应，具有接触两个以上的电极的两个以上的接触端子的第一片; 电连接到所述两个或更多个接触端子和所述第一布线的第二布线; 并且在两个或多个接触端子的形成区域附近的第一虚拟布线被布置到第二布线的非形成区域，并且不参与信号传递。