公开(公告)号：US11316027B2

公开(公告)日：2022-04-26

申请号：US16833375

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Sou-Chi Chang ,  Chia-Ching Lin ,  Nazila Haratipour ,  Tanay Gosavi ,  I-Cheng Tung ,  Seung Hoon Sung ,  Ian Young ,  Jack Kavalieros ,  Uygar Avci ,  Ashish Verma Penumatcha

IPC: H01L21/02 ,  H01L29/51 ,  H01L29/24 ,  H01L29/92

Abstract: A capacitor device includes a first electrode having a first metal alloy or a metal oxide, a relaxor ferroelectric layer adjacent to the first electrode, where the ferroelectric layer includes oxygen and two or more of lead, barium, manganese, zirconium, titanium, iron, bismuth, strontium, neodymium, potassium, or niobium and a second electrode coupled with the relaxor ferroelectric layer, where the second electrode includes a second metal alloy or a second metal oxide.

公开(公告)号：US11264512B2

公开(公告)日：2022-03-01

申请号：US16024682

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Aaron Lilak ,  Van H. Le ,  Abhishek A. Sharma ,  Tahir Ghani ,  Willy Rachmady ,  Rishabh Mehandru ,  Nazila Haratipour ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Shriram Shivaraman

IPC: H01L29/786 ,  H01L29/66

Abstract: Thin film transistors having U-shaped features are described. In an example, integrated circuit structure including a gate electrode above a substrate, the gate electrode having a trench therein. A channel material layer is over the gate electrode and in the trench, the channel material layer conformal with the trench. A first source or drain contact is coupled to the channel material layer at a first end of the channel material layer outside of the trench. A second source or drain contact is coupled to the channel material layer at a second end of the channel material layer outside of the trench.

公开(公告)号：US11138499B2

公开(公告)日：2021-10-05

申请号：US16147176

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Abhishek Sharma ,  Jack T. Kavalieros ,  Ian A. Young ,  Sasikanth Manipatruni ,  Ram Krishnamurthy ,  Uygar Avci ,  Gregory K. Chen ,  Amrita Mathuriya ,  Raghavan Kumar ,  Phil Knag ,  Huseyin Ekin Sumbul ,  Nazila Haratipour ,  Van H. Le

IPC: G06N3/063 ,  H01L27/108 ,  H01L27/11502 ,  G06N3/04 ,  G06F17/16 ,  H01L27/11 ,  G11C11/54 ,  G11C7/10 ,  G11C11/419 ,  G11C11/409 ,  G11C11/22

Abstract: An apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The memory array includes an embedded dynamic random access memory (eDRAM) memory array. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes a switched capacitor circuit. The switched capacitor circuit includes a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within the metal/dielectric layers of the semiconductor chip. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes an accumulation circuit. The accumulation circuit includes a ferroelectric BEOL capacitor to store a value to be accumulated with other values stored by other ferroelectric BEOL capacitors.

公开(公告)号：US20200286687A1

公开(公告)日：2020-09-10

申请号：US16296085

申请日：2019-03-07

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Sou-Chi Chang ,  Nazila Haratipour ,  Seung Hoon Sung ,  Ashish Verma Penumatcha ,  Jack Kavalieros ,  Uygar E. Avci ,  Ian A. Young

IPC: H01G7/06 ,  H01L27/108 ,  H01L49/02 ,  G11C11/22

Abstract: Described is an ultra-dense ferroelectric memory. The memory is fabricated using a patterning method by that applies atomic layer deposition with selective dry and/or wet etch to increase memory density at a given via opening. A ferroelectric capacitor in one example comprises: a first structure (e.g., first electrode) comprising metal; a second structure (e.g., a second electrode) comprising metal; and a third structure comprising ferroelectric material, wherein the third structure is between and adjacent to the first and second structures, wherein a portion of the third structure is interdigitated with the first and second structures to increase surface area of the third structure. The increased surface area allows for higher memory density.

公开(公告)号：US12170319B2

公开(公告)日：2024-12-17

申请号：US17033362

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Kevin Cook ,  Anand S. Murthy ,  Gilbert Dewey ,  Nazila Haratipour ,  Ralph Thomas Troeger ,  Christopher J. Jezewski ,  I-Cheng Tung

IPC: H01L29/417 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/40 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

Abstract: Embodiments disclosed herein include complementary metal-oxide-semiconductor (CMOS) devices and methods of forming CMOS devices. In an embodiment, a CMOS device comprises a first transistor with a first conductivity type, where the first transistor comprises a first source region and a first drain region, and a first metal over the first source region and the first drain region. In an embodiment, the CMOS device further comprises a second transistor with a second conductivity type opposite form the first conductivity type, where the second transistor comprises a second source region and a second drain region, a second metal over the second source region and the second drain region, and the first metal over the second metal.

公开(公告)号：US12166122B2

公开(公告)日：2024-12-10

申请号：US17133197

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Shriram Shivaraman ,  Uygar Avci ,  Ashish Verma Penumatcha ,  Nazila Haratipour ,  Seung Hoon Sung ,  Sou-Chi Chang

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H10B51/30

Abstract: A memory device structure includes a transistor structure including a gate electrode over a top surface of a fin and adjacent to a sidewall of the fin, a source structure coupled to a first region of the fin and a drain structure coupled to a second region of the fin, where the gate electrode is between the first and the second region. A gate dielectric layer is between the fin and the gate electrode. The memory device structure further includes a capacitor coupled with the transistor structure, the capacitor includes the gate electrode, a ferroelectric layer on a substantially planar uppermost surface of the gate electrode and a word line on the ferroelectric layer.

公开(公告)号：US12119387B2

公开(公告)日：2024-10-15

申请号：US17033471

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Nazila Haratipour ,  Siddharth Chouksey ,  Jack T. Kavalieros ,  Jitendra Kumar Jha ,  Matthew V. Metz ,  Mengcheng Lu ,  Anand S. Murthy ,  Koustav Ganguly ,  Ryan Keech ,  Glenn A. Glass ,  Arnab Sen Gupta

IPC: H01L29/45 ,  H01L21/285 ,  H01L21/768 ,  H01L23/485 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/45 ,  H01L21/28518 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696

Abstract: Low resistance approaches for fabricating contacts, and semiconductor structures having low resistance metal contacts, are described. In an example, an integrated circuit structure includes a semiconductor structure above a substrate. A gate electrode is over the semiconductor structure, the gate electrode defining a channel region in the semiconductor structure. A first semiconductor source or drain structure is at a first end of the channel region at a first side of the gate electrode. A second semiconductor source or drain structure is at a second end of the channel region at a second side of the gate electrode, the second end opposite the first end. A source or drain contact is directly on the first or second semiconductor source or drain structure, the source or drain contact including a barrier layer and an inner conductive structure.

公开(公告)号：US20240006488A1

公开(公告)日：2024-01-04

申请号：US17856620

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  Gilbert Dewey ,  Nancy Zelick ,  Siddharth Chouksey ,  I-Cheng Tung ,  Arnab Sen Gupta ,  Jitendra Kumar Jha ,  David Kohen ,  Natalie Briggs ,  Chi-Hing Choi ,  Matthew V. Metz ,  Jack T. Kavalieros

IPC: H01L29/08 ,  H01L27/088 ,  H01L29/417 ,  H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L21/033

CPC classification number: H01L29/0847 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/7851 ,  H01L29/401 ,  H01L29/66795 ,  H01L21/0332

Abstract: In one embodiment, layers comprising Carbon (e.g., Silicon Carbide) are on source/drain regions of a transistor, e.g., before gate formation and metallization, and the layers comprising Carbon are later removed in the manufacturing process to form electrical contacts on the source/drain regions.

公开(公告)号：US11843058B2

公开(公告)日：2023-12-12

申请号：US17516569

申请日：2021-11-01

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Abhishek Sharma ,  Van Le ,  Jack Kavalieros ,  Shriram Shivaraman ,  Seung Hoon Sung ,  Tahir Ghani ,  Arnab Sen Gupta ,  Nazila Haratipour ,  Justin Weber

IPC: H01L29/786 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/221

CPC classification number: H01L29/7869 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/221 ,  H01L29/78696

Abstract: Transistor structures may include a metal oxide contact buffer between a portion of a channel material and source or drain contact metallization. The contact buffer may improve control of transistor channel length by limiting reaction between contact metallization and the channel material. The channel material may be of a first composition and the contact buffer may be of a second composition.

公开(公告)号：US11843054B2

公开(公告)日：2023-12-12

申请号：US16016381

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Van H. Le ,  Seung Hoon Sung ,  Benjamin Chu-Kung ,  Miriam Reshotko ,  Matthew Metz ,  Yih Wang ,  Gilbert Dewey ,  Jack Kavalieros ,  Tahir Ghani ,  Nazila Haratipour ,  Abhishek Sharma ,  Shriram Shivaraman

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/423 ,  H01L23/522 ,  H01L29/66 ,  H01L29/49 ,  H10B12/00

CPC classification number: H01L29/78642 ,  H01L23/5226 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/78603 ,  H01L29/78645 ,  H10B12/05 ,  H10B12/30

Abstract: Embodiments herein describe techniques for a semiconductor device including a transistor. The transistor includes a first metal contact as a source electrode, a second metal contact as a drain electrode, a channel area between the source electrode and the drain electrode, and a third metal contact aligned with the channel area as a gate electrode. The first metal contact may be located in a first metal layer along a first direction. The second metal contact may be located in a second metal layer along the first direction, in parallel with the first metal contact. The third metal contact may be located in a third metal layer along a second direction substantially orthogonal to the first direction. The third metal layer is between the first metal layer and the second metal layer. Other embodiments may be described and/or claimed.