公开(公告)号：US20060017161A1

公开(公告)日：2006-01-26

申请号：US11186964

申请日：2005-07-22

申请人： Jae-Sik Chung ,  Se-Young Jeong ,  Dong-Hyeon Jang

发明人： Jae-Sik Chung ,  Se-Young Jeong ,  Dong-Hyeon Jang

IPC分类号： H01L21/44 ,  H01L23/48

CPC分类号： H01L21/76838 ,  H01L23/3114 ,  H01L23/3157 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05671 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/062 ,  H05K3/108 ,  H05K3/244 ,  H05K3/388 ,  H05K2203/0505 ,  H05K2203/0597 ,  H01L2924/00 ,  H01L2924/00014

摘要： An apparatus and method for manufacturing a semiconductor package are disclosed. The apparatus may include at least a semiconductor chip having input/output (I/O) pads arranged on a surface thereof, a first dielectric layer formed on the surface of the semiconductor chip which may expose the I/O pads, a seed metal layer selectively formed on the first dielectric layer and the I/O pads, re-routing lines formed on the seed metal layer and electrically coupled to the I/O pads, a protective coating layer on side surfaces and an upper surface of each re-routing line, a second dielectric layer formed on the first dielectric layer which may cover the re-routing lines surrounded with the protective coating layer, and solder balls formed on the respective pads and electrically coupled to the re-routing lines.

摘要翻译： 公开了一种用于制造半导体封装的装置和方法。 该装置可以包括至少一个具有布置在其表面上的输入/输出（I / O）焊盘的半导体芯片，形成在半导体芯片的可能暴露I / O焊盘的表面上的第一介电层，种子金属层 选择性地形成在第一电介质层和I / O焊盘上，形成在种子金属层上并电耦合到I / O焊盘的再布线，在每个重新路由的侧表面上的保护涂层和上表面 形成在第一电介质层上的第二电介质层，其可以覆盖被保护涂层包围的重路由线，以及形成在相应焊盘上并电耦合到重路由线的焊球。

公开(公告)号：US20050090089A1

公开(公告)日：2005-04-28

申请号：US10911672

申请日：2004-08-05

申请人： Keum-Hee Ma ,  Se-Young Jeong ,  Dong-Hyeon Jang ,  Gu-Sung Kim

发明人： Keum-Hee Ma ,  Se-Young Jeong ,  Dong-Hyeon Jang ,  Gu-Sung Kim

IPC分类号： H01L21/60 ,  H01L21/44 ,  H01L23/485 ,  H01L23/50

CPC分类号： H01L24/12 ,  H01L24/11 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1147 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00014

摘要： A solder bump structure may be formed using a dual exposure technique of a photoresist, which may be a positive photoresist. The positive photoresist may be coated on an IC chip. First openings may be formed at first exposed regions of the photoresist by a first exposure process. Metal projections may be formed in the first openings. A second opening may be formed at a second exposed region of the photoresist by a second exposure process. The second exposed region may include non-exposed regions defined by the first exposure process. A solder material may fill the second opening and may be reflowed to form a solder bump. The metal projections may be embedded within the solder bump.

摘要翻译： 可以使用可以是正性光致抗蚀剂的光致抗蚀剂的双曝光技术来形成焊料凸块结构。 正光致抗蚀剂可以涂覆在IC芯片上。 可以通过第一曝光工艺在光致抗蚀剂的第一曝光区域处形成第一开口。 金属突起可以形成在第一开口中。 可以通过第二曝光工艺在光致抗蚀剂的第二曝光区域处形成第二开口。 第二曝光区域可以包括由第一曝光工艺限定的非曝光区域。 焊料材料可以填充第二开口并且可以回流以形成焊料凸块。 金属突起可以嵌入在焊料凸块内。

公开(公告)号：US20050046002A1

公开(公告)日：2005-03-03

申请号：US10890995

申请日：2004-07-15

申请人： Kang-Wook Lee ,  Gu-Sung Kim ,  Dong-Hyeon Jang ,  Seung-Duk Baek ,  Jae-Sik Chung

发明人： Kang-Wook Lee ,  Gu-Sung Kim ,  Dong-Hyeon Jang ,  Seung-Duk Baek ,  Jae-Sik Chung

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/98 ,  H01L23/48 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L21/44 ,  H01L21/48 ,  H01L23/02

CPC分类号： H01L25/50 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/48 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05556 ,  H01L2224/05569 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  Y02P80/30 ,  Y10S438/977 ,  Y10T436/104998 ,  Y10T436/108331 ,  Y10T436/17 ,  Y10T436/175383 ,  H01L2224/81 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A chip stack package is manufactured at a wafer level by forming connection vias in the scribe lanes adjacent the chips and connecting the device chip pads to the connection vias using rerouting lines. A lower chip is then attached and connected to a substrate, which may be a test wafer, and an upper chip is attached and connected to the lower chip, the electrical connections being achieved through their respective connection vias. In addition to the connection vias, the chip stack package may include connection bumps formed between vertically adjacent chips and/or the lower chip and the substrate. The preferred substrate is a test wafer that allows the attached chips to be tested, and replaced if faulty, thereby ensuring that each layer of stacked chips includes only “known-good die” before the next layer of chips is attached thereby increasing the production rate and improving the yield.

摘要翻译： 通过在与芯片相邻的划线中形成连接通孔并且使用重新布线将连接器件芯片焊盘连接到连接通孔，在晶片级制造芯片堆叠封装。 然后将下部芯片连接并连接到可以是测试晶片的衬底，并且上部芯片被附接并连接到下部芯片，电连接通过它们各自的连接通孔来实现。 除了连接通孔之外，芯片堆叠封装可以包括在垂直相邻的芯片和/或下部芯片和衬底之间形成的连接凸块。 优选的基板是测试晶片，其允许附接的芯片被测试并且如果有故障则被替换，从而确保每层堆叠的芯片仅在连接下一层芯片之前仅包括“已知的芯片”，从而提高生产率 并提高产量。

公开(公告)号：US06836018B2

公开(公告)日：2004-12-28

申请号：US10304264

申请日：2002-11-25

申请人： Gu-Sung Kim ,  Dong-Hyeon Jang ,  Min-Young Son ,  Sa-Yoon Kang

发明人： Gu-Sung Kim ,  Dong-Hyeon Jang ,  Min-Young Son ,  Sa-Yoon Kang

IPC分类号： H01L2348

CPC分类号： H01L24/10 ,  H01L23/3157 ,  H01L23/34 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05555 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/351 ,  H05K1/0271 ,  H05K3/3436 ,  H01L2924/00

摘要： A thermal-stress-absorbing interface structure is provided between a semiconductor integrated circuit chip and a surface-mount structure. The interface structure comprises an elongated conductive-bump pad having a first length-wise end and a second length-wise end, and a side. The pad has an interconnection line extending from the side thereof intermediate the first and the second ends. The interconnection line is electrically connected to the chip. The interface structure further includes a first polymer layer having an exposed surface, and a second polymer layer, each having a different modulus of elasticity, disposed below the pad. The second polymer layer extends over substantially the entire exposed surface of the first polymer layer to absorb a thermal stress during thermal cycling.

摘要翻译： 在半导体集成电路芯片和表面安装结构之间提供热应力吸收界面结构。 界面结构包括具有第一纵向端和第二纵向端以及侧面的细长导电凸块垫。 垫具有从第一端和第二端的中间的一侧延伸的互连线。 互连线电连接到芯片。 界面结构还包括设置在垫下方的具有暴露表面的第一聚合物层和每个具有不同弹性模量的第二聚合物层。 第二聚合物层在第一聚合物层的基本上整个暴露的表面上延伸以在热循环期间吸收热应力。

公开(公告)号：US06586275B2

公开(公告)日：2003-07-01

申请号：US10103630

申请日：2002-03-20

申请人： Gu-Sung Kim ,  Dong-Hyeon Jang ,  Min-Young Son ,  Sa-Yoon Kang

发明人： Gu-Sung Kim ,  Dong-Hyeon Jang ,  Min-Young Son ,  Sa-Yoon Kang

IPC分类号： H01L2144

CPC分类号： H01L24/10 ,  H01L23/3157 ,  H01L23/34 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05555 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/351 ,  H05K1/0271 ,  H05K3/3436 ,  H01L2924/00

摘要： A thermal-stress-absorbing interface structure between a semiconductor integrated circuit chip and a surface-mount structure and a method for manufacturing the same. The thermal-stress-absorbing interface structure comprises an elongated conductive-bump pad having a first length-wise end and a second length-wise end, and a side. The thermal-stress-absorbing interface structure includes means for allowing the first end of the pad to move up when the second end of the pad moves down and alternately allowing the first end to move down when the second end moves up, upon thermal cycling. The means has a center axis and the up-and-down movements of the pad are balanced on the center axis. In accordance with this novel structure of the present invention, interconnection reliability such as solder joint reliability can be significantly improved.

摘要翻译： 半导体集成电路芯片和表面安装结构之间的热应力吸收界面结构及其制造方法。 热应力吸收界面结构包括具有第一纵向端和第二纵向端以及侧面的细长导电凸块焊盘。 所述热应力吸收界面结构包括当所述垫的第二端向下移动时允许所述垫的第一端向上移动的装置，并且当热循环时，当所述第二端向上移动时交替允许所述第一端向下移动。 该装置具有中心轴线，并且垫片的上下运动在中心轴线上平衡。根据本发明的这种新颖结构，可以显着提高诸如焊点可靠性之类的互连可靠性。