公开(公告)号：US09679843B2

公开(公告)日：2017-06-13

申请号：US15049500

申请日：2016-02-22

Applicant: Intel Corporation

Inventor： Robert Starkston ,  Debendra Mallik ,  John S. Guzek ,  Chia-Pin Chiu ,  Deepak Kulkarni ,  Ravindranath V. Mahajan

IPC: H01L23/48 ,  H01L23/522 ,  H01L25/00 ,  H01L23/538 ,  H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L23/5226 ,  H01L21/563 ,  H01L23/5385 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/05568 ,  H01L2224/0603 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/83102 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/014 ,  H01L2924/00

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

公开(公告)号：US20160197037A1

公开(公告)日：2016-07-07

申请号：US15049500

申请日：2016-02-22

Applicant: Intel Corporation

Inventor： Robert Starkston ,  Debendra Mallik ,  John S. Guzek ,  Chia-Pin Chiu ,  Deepak Kulkarni ,  Ravindranath V. Mahajan

IPC: H01L23/522 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/5226 ,  H01L21/563 ,  H01L23/5385 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/05568 ,  H01L2224/0603 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/83102 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/014 ,  H01L2924/00

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

公开(公告)号：US20240329301A1

公开(公告)日：2024-10-03

申请号：US18130052

申请日：2023-04-03

Applicant: Intel Corporation

Inventor： Kaveh Hosseini ,  Ravindranath V. Mahajan ,  Chia-Pin Chiu

IPC: G02B6/12

CPC classification number: G02B6/12004

Abstract: A substrate for a multi-chip package includes at least one photonic integrated circuit (PIC) interposer mounted in a cavity in a first major surface. Each PIC interposer is configured to electrically connect with, or optically couple to, a plurality of integrated circuit devices. The substrate further includes at least one optical coupler that is optically coupled to the PIC interposer.

公开(公告)号：US11901299B2

公开(公告)日：2024-02-13

申请号：US18079753

申请日：2022-12-12

Applicant: Intel Corporation

Inventor： Md Altaf Hossain ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy ,  Robert Sankman ,  Ravindranath V. Mahajan ,  Debendra Mallik ,  Ram S. Viswanath ,  Sandeep B. Sane ,  Sriram Srinivasan ,  Rajat Agarwal ,  Aravind Dasu ,  Scott Weber ,  Ravi Gutala

IPC: H01L23/538 ,  H01L25/18 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/17 ,  H01L25/18 ,  H01L23/481 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2924/381

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.

公开(公告)号：US11894359B2

公开(公告)日：2024-02-06

申请号：US17574485

申请日：2022-01-12

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Mark T. Bohr ,  Rajesh Kumar ,  Robert L. Sankman ,  Ravindranath V. Mahajan ,  Wesley D. McCullough

IPC: H01L23/00 ,  H01L25/18 ,  H01L23/48 ,  H01L25/00 ,  H01L23/538 ,  H01L23/522 ,  H01L25/16 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L25/18 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5383 ,  H01L24/09 ,  H01L24/17 ,  H01L25/0652 ,  H01L25/16 ,  H01L25/50 ,  H01L23/49816 ,  H01L2924/1432

Abstract: The present disclosure is directed to systems and methods of conductively coupling a plurality of relatively physically small core dies to a relatively physically larger base die using an electrical mesh network that is formed in whole or in part in, on, across, or about all or a portion of the base die. Electrical mesh networks beneficially permit the positioning of the cores in close proximity to support circuitry carried by the base die. The minimal separation between the core circuitry and the support circuitry advantageously improves communication bandwidth while reducing power consumption. Each of the cores may include functionally dedicated circuitry such as processor core circuitry, field programmable logic, memory, or graphics processing circuitry. The use of core dies beneficially and advantageously permits the use of a wide variety of cores, each having a common or similar interface to the electrical mesh network.

公开(公告)号：US11830863B2

公开(公告)日：2023-11-28

申请号：US17539088

申请日：2021-11-30

Applicant: Intel Corporation

Inventor： Suresh V. Pothukuchi ,  Andrew Alduino ,  Ravindranath V. Mahajan ,  Srikant Nekkanty ,  Ling Liao ,  Harinadh Potluri ,  David M. Bond ,  Sushrutha Reddy Gujjula ,  Donald Tiendung Tran ,  David Hui ,  Vladimir Tamarkin

IPC: H01L25/16 ,  H01L23/367 ,  H01L23/40 ,  H01L23/473 ,  H01L23/538 ,  H04Q11/00

CPC classification number: H01L25/167 ,  H01L23/367 ,  H01L23/40 ,  H01L23/4006 ,  H01L23/473 ,  H01L23/5385 ,  H01L23/5386 ,  H04Q11/0005 ,  H01L2023/4031 ,  H04Q2011/0039

Abstract: Embodiments disclosed herein include electronic packages for optical to electrical switching. In an embodiment, an electronic package comprises a first package substrate and a second package substrate attached to the first package substrate. In an embodiment, a die is attached to the second package substrate. In an embodiment, a plurality of photonics engines are attached to a first surface and a second surface of the first package substrate. In an embodiment, the plurality of photonics engines are communicatively coupled to the die through the first package substrate and the second package substrate.

公开(公告)号：US20230317619A1

公开(公告)日：2023-10-05

申请号：US17711978

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Ravindranath V. Mahajan ,  Srikant Nekkanty ,  Srinivas V. Pietambaram ,  Veronica Strong ,  Xiao Lu ,  Tarek A. Ibrahim ,  Karumbu Nathan Meyyappan ,  Dingying Xu ,  Kristof Darmawikarta

IPC: H01L23/538 ,  H01L21/48

CPC classification number: H01L23/5381 ,  H01L21/486 ,  H01L23/5384

Abstract: A microelectronic structure, a semiconductor package including the same, and a method of forming same. The microelectronic structures includes: a substrate defining a cavity therein; a bridge die within the cavity, the bridge die to electrically couple a pair of dies to be provided on a surface of the substrate; an electrical coupling layer between a top surface of the cavity and a bottom surface of the bridge die. The electrical coupling layer includes: a non-conductive component including a die bonding film and defining holes therein; and electrically conductive structures in the holes, the electrically conductive structures electrically coupling the substrate with the bridge die.

公开(公告)号：US11694959B2

公开(公告)日：2023-07-04

申请号：US16524748

申请日：2019-07-29

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Kevin McCarthy ,  Leigh M. Tribolet ,  Debendra Mallik ,  Ravindranath V. Mahajan ,  Robert L. Sankman

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/5381 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a bridge over a glass patch. The bridge is coupled to the glass patch with an adhesive layer. The semiconductor package also includes a high-density packaging (HDP) substrate over the bridge and the glass patch. The HDP substrate is conductively coupled to the glass patch with a plurality of through mold vias (TMVs). The semiconductor package further includes a plurality of dies over the HDP substrate, and a first encapsulation layer over the TMVs, the bridge, the adhesive layer, and the glass patch. The HDP substrate includes a plurality of conductive interconnects that conductively couple the dies to the bridge and glass patch. The bridge may be an embedded multi-die interconnect bridge (EMIB), where the EMIB is communicatively coupled to the dies, and the glass patch includes a plurality of through glass vias (TGVs).

公开(公告)号：US20190318993A1

公开(公告)日：2019-10-17

申请号：US16469084

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Ravindranath V. Mahajan ,  Zhiguo Qian ,  Henning Braunisch ,  Kemal Aygun ,  Sujit Sharan

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L25/00

Abstract: A device and method of utilizing a repeater circuit to extend the viable length of an interconnect bridge. Integrated circuit packages using a repeater circuit in a repeater die, embedded in a substrate, and included in an interconnect bridge are show. Methods of connecting semiconductor dies using interconnect bridges coupled with repeater circuits are shown.

公开(公告)号：US20190304809A1

公开(公告)日：2019-10-03

申请号：US15937453

申请日：2018-03-27

Applicant: Intel Corporation

Inventor： Digvijay Ashokkumar Raorane ,  Ravindranath V. Mahajan

IPC: H01L21/56 ,  H01L21/683 ,  H01L21/68 ,  H01L21/66 ,  H01L23/00 ,  H01L25/065 ,  H01L23/538

Abstract: A method of aligning semiconductor dies having metallic bumps in a mold chase for further processing. A plurality of semiconductor dies are placed in the mold chase at approximately desired locations for further processing. A plurality of magnets in a retainer are associated with the mold chase, the plurality of magnets being associated with respective ones of the plurality of semiconductor dies. The magnetic field of the magnets is applied to align and hold the plurality of dies at the desired location. The plurality of magnets may be adjustably mounted in the retainer so that they can be adjusted to more precisely align the semiconductor dies at the desired locations.