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    Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages
    41.
    发明授权
    Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages 有权

    公开(公告)号：US10177083B2

    公开(公告)日：2019-01-08

    申请号：US15749462

    申请日：2015-10-29

    Applicant: Intel Corporation

    Inventor： Dae-Woo Kim ,  Sujit Sharan

    IPC: H01L23/498 ,  H01L23/13 ,  H01L23/00 ,  H01L23/48

    Abstract: Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having a lower insulating layer disposed thereon. The substrate has a perimeter. A metallization structure is disposed on the lower insulating layer. The metallization structure includes conductive routing disposed in a dielectric material stack. First and second pluralities of conductive pads are disposed in a plane above the metallization structure. Conductive routing of the metallization structure electrically connects the first plurality of conductive pads with the second plurality of conductive pads. An upper insulating layer is disposed on the first and second pluralities of conductive pads. The upper insulating layer has a perimeter substantially the same as the perimeter of the substrate.

    PROJECTING CONTACTS AND METHOD FOR MAKING THE SAME
    42.
    发明申请
    PROJECTING CONTACTS AND METHOD FOR MAKING THE SAME 审中-公开

    公开(公告)号：US20180366438A1

    公开(公告)日：2018-12-20

    申请号：US15781998

    申请日：2015-12-22

    Applicant: Intel Corporation

    Inventor： Dae-Woo Kim ,  Sujit Sharan ,  Ravindranath V. Mahajan

    IPC: H01L25/065 ,  H01L23/538 ,  H01L23/498 ,  H01L23/31 ,  H01L25/00

    Abstract: A package assembly includes a substrate extending from a first substrate end to a second substrate end. A plurality of conductive traces extend along the substrate. A plurality of contacts are coupled with the respective conductive traces of the plurality of conductive traces. Each of the contacts of the plurality of contacts includes a contact pad coupled with a respective conductive trace of the plurality of conductive traces, and a contact post coupled with the contact pad, the contact post extends from the contact pad. A package cover layer is coupled over the plurality of contact posts. The plurality of contact posts are configured to penetrate the package cover layer and extend to a raised location above the package cover layer.

    Metal-free frame design for silicon bridges for semiconductor packages
    44.
    发明授权
    Metal-free frame design for silicon bridges for semiconductor packages 有权

    公开(公告)号：US12170253B2

    公开(公告)日：2024-12-17

    申请号：US18114123

    申请日：2023-02-24

    Applicant: Intel Corporation

    Inventor： Dae-Woo Kim ,  Sujit Sharan ,  Sairam Agraharam

    IPC: H01L23/538 ,  G01R31/27 ,  H01L21/66 ,  H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L23/544 ,  H01L23/58 ,  H01L23/14 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

    Abstract: Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.

    INTERCONNECT BRIDGE CIRCUITRY DESIGNS FOR INTEGRATED CIRCUIT PACKAGE SUBSTRATES
    46.
    发明公开
    INTERCONNECT BRIDGE CIRCUITRY DESIGNS FOR INTEGRATED CIRCUIT PACKAGE SUBSTRATES 审中-公开

    公开(公告)号：US20240332193A1

    公开(公告)日：2024-10-03

    申请号：US18192804

    申请日：2023-03-30

    Applicant: Intel Corporation

    Inventor： Lijiang Wang ,  Sujit Sharan

    IPC: H01L23/538

    CPC classification number: H01L23/5381 ,  H01L23/5386

    Abstract: In one embodiment, an interconnect bridge circuitry includes a first set of bridge-to-die electrical connectors in a first region of the circuitry, a second set of bridge-to-die electrical connectors in a second region of the circuitry, and an interconnection between a bridge-to-die connector of the first set and a bridge-to-die connector of the second set. The interconnection is in a third region of the circuitry between the first region and the second region, and includes a first trace connected to the bridge-to-die electrical connector of the first set, a second trace connected to the bridge-to-die electrical connector of the second set, the second trace parallel with the first trace, and a third trace connected between the first trace and the second trace.

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