公开(公告)号：US20140054548A1

公开(公告)日：2014-02-27

申请号：US14069880

申请日：2013-11-01

申请人： Ravi Pillarisetty ,  Jack T. Kavalieros ,  Willy Rachmady ,  Uday Shah ,  Benjamin Chu-Kung ,  Marko Radosavljevic ,  Niloy Mukherjee ,  Gilbert Dewey ,  Been-Yih Jin ,  Robert S. Chau

发明人： Ravi Pillarisetty ,  Jack T. Kavalieros ,  Willy Rachmady ,  Uday Shah ,  Benjamin Chu-Kung ,  Marko Radosavljevic ,  Niloy Mukherjee ,  Gilbert Dewey ,  Been-Yih Jin ,  Robert S. Chau

IPC分类号： H01L29/775 ,  H01L21/76 ,  H01L29/66

CPC分类号： H01L29/775 ,  B82Y10/00 ,  H01L21/76 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/66977 ,  H01L29/7782 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851

摘要： Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

公开(公告)号：US20140008700A1

公开(公告)日：2014-01-09

申请号：US13996502

申请日：2011-12-23

申请人： Willy Rachmady ,  Van H. Le ,  Ravi Pillarisetty ,  Jack T. Kavalieros ,  Robert S. Chau ,  Harold W. Kennel

发明人： Willy Rachmady ,  Van H. Le ,  Ravi Pillarisetty ,  Jack T. Kavalieros ,  Robert S. Chau ,  Harold W. Kennel

IPC分类号： H01L29/06

CPC分类号： H01L29/1083 ,  B82Y10/00 ,  H01L21/28255 ,  H01L29/0603 ,  H01L29/0607 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7781 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78603 ,  H01L29/78684 ,  H01L29/78696

摘要： Semiconductor devices having germanium active layers with underlying diffusion barrier layers are described. For example, a semiconductor device includes a gate electrode stack disposed above a substrate. A germanium active layer is disposed above the substrate, underneath the gate electrode stack. A diffusion barrier layer is disposed above the substrate, below the germanium active layer. A junction leakage suppression layer is disposed above the substrate, below the diffusion barrier layer. Source and drain regions are disposed above the junction leakage suppression layer, on either side of the gate electrode stack.

摘要翻译： 描述具有底层扩散阻挡层的锗活性层的半导体器件。 例如，半导体器件包括设置在衬底上方的栅极电极堆叠。 锗基活性层设置在基板上方，栅电极堆叠下方。 扩散阻挡层设置在基底上方，在锗活性层下方。 接点泄漏抑制层设置在基底上方，在扩散阻挡层下方。 源极和漏极区域设置在栅极电极堆叠的任一侧上的结泄漏抑制层上方。

公开(公告)号：US20100327377A1

公开(公告)日：2010-12-30

申请号：US12459254

申请日：2009-06-26

申请人： Gilbert Dewey ,  Niloy Mukherjee ,  Matthew Metz ,  Jack T. Kavalieros ,  Nancy M. Zelick ,  Robert S. Chau

发明人： Gilbert Dewey ,  Niloy Mukherjee ,  Matthew Metz ,  Jack T. Kavalieros ,  Nancy M. Zelick ,  Robert S. Chau

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L21/31 ,  H01L21/3205

CPC分类号： H01L29/517 ,  H01B1/122 ,  H01L21/048 ,  H01L21/28525 ,  H01L21/324 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76841 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/53266 ,  H01L29/45 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/518 ,  H01L29/66643 ,  H01L29/7839 ,  H01L29/7853 ,  H01L31/022466 ,  H01L31/022475 ,  H01L33/0041 ,  H01L33/40 ,  H01L45/08 ,  H01L45/1206 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/145 ,  H01L51/102 ,  H01L51/105 ,  H01L51/441 ,  H01L51/442 ,  H01L51/5203 ,  H01L51/5234 ,  H01L2251/301 ,  H01L2251/303 ,  H01L2251/306 ,  H01L2251/308 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.

摘要翻译： 使用中间层来减少具有半导体衬底的半导体器件中的费米能级钉扎现象。 中间层可以是稀土氧化物。 中间层可以是离子半导体。 金属阻挡膜可以设置在中间层和金属耦合器之间。 中间层可以是金属阻挡膜和半导体基板的热处理组合。 形成中间层的方法可以包括对中间层进行分级。 计算系统包括中间层。

公开(公告)号：US07767560B2

公开(公告)日：2010-08-03

申请号：US11864963

申请日：2007-09-29

申请人： Been-Yih Jin ,  Robert S. Chau ,  Brian S. Doyle ,  Jack T. Kavalieros

发明人： Been-Yih Jin ,  Robert S. Chau ,  Brian S. Doyle ,  Jack T. Kavalieros

IPC分类号： H01L21/36 ,  H01L21/20

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02664 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/66818 ,  H01L29/7851

摘要： The present disclosure describes a method and apparatus for implementing a 3D (three dimensional) strained high mobility quantum well structure, and a 3D strained surface channel structure through a Ge confinement method. One exemplary apparatus may include a first graded SiGe fin on a Si substrate. The first graded SiGe fin may have a maximum Ge concentration greater than about 60%. A Ge quantum well may be on the first graded SiGe fin and a SiGe quantum well upper barrier layer may be on the Ge quantum well. The exemplary apparatus may further include a second graded SiGe fin on the Si substrate. The second graded SiGe fin may have a maximum Ge concentration less than about 40%. A Si active channel layer may be on the second graded SiGe fin. Other high mobility materials such as III-V semiconductors may be used as the active channel materials. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

摘要翻译： 本公开描述了通过Ge约束法实现3D（三维）应变高迁移量子阱结构和3D应变表面通道结构的方法和装置。 一个示例性设备可以包括在Si衬底上的第一梯度SiGe鳍。 第一级的SiGe鳍可以具有大于约60％的最大Ge浓度。 Ge量子阱可以在第一等级的SiGe鳍上，SiGe量子阱上阻挡层可以在Ge量子阱上。 示例性设备还可以包括在Si衬底上的第二渐变SiGe鳍。 第二级的SiGe鳍可以具有小于约40％的最大Ge浓度。 Si活性沟道层可以在第二级别的SiGe鳍上。 可以使用诸如III-V族半导体的其它高迁移率材料作为活性通道材料。 当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

公开(公告)号：US07727830B2

公开(公告)日：2010-06-01

申请号：US12006273

申请日：2007-12-31

申请人： Been-Yih Jin ,  Jack T. Kavalieros ,  Matthew V. Metz ,  Marko Radosavlievic ,  Robert S. Chau

发明人： Been-Yih Jin ,  Jack T. Kavalieros ,  Matthew V. Metz ,  Marko Radosavlievic ,  Robert S. Chau

IPC分类号： H01L21/337

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/42392 ,  H01L29/66477 ,  H01L29/78684 ,  H01L29/78696

摘要： In general, in one aspect, a method includes using the Germanium nanowire as building block for high performance logic, memory and low dimensional quantum effect devices. The Germanium nanowire channel and the SiGe anchoring regions are formed simultaneously through preferential Si oxidation of epitaxial Silicon Germanium epi layer. The placement of the germanium nanowires is accomplished using a Si fin as a template and the germanium nanowire is held on Si substrate through SiGe anchors created by masking the two ends of the fins. High dielectric constant gate oxide and work function metals wrap around the Germanium nanowire for gate-all-around electrostatic channel on/off control, while the Germanium nanowire provides high carrier mobility in the transistor channel region. The germanium nanowire transistors enable high performance, low voltage (low power consumption) operation of logic and memory devices.

摘要翻译： 通常，在一个方面，一种方法包括使用锗纳米线作为高性能逻辑，存储器和低维量子效应器件的构建块。 锗纳米线通道和SiGe锚定区域通过外延硅锗外延层的优先Si氧化同时形成。 使用Si翅片作为模板来实现锗纳米线的放置，并且锗纳米线通过掩蔽翅片的两端而形成的SiGe锚定件保持在Si衬底上。 高介电常数栅极氧化物和功函数金属缠绕在锗纳米线上，用于门极全静电通道开/关控制，而锗纳米线在晶体管沟道区域提供高载流子迁移率。 锗纳米线晶体管可实现逻辑和存储器件的高性能，低电压（低功耗）操作。

公开(公告)号：US09608055B2

公开(公告)日：2017-03-28

申请号：US13996502

申请日：2011-12-23

申请人： Willy Rachmady ,  Van H. Le ,  Ravi Pillarisetty ,  Jack T. Kavalieros ,  Robert S. Chau ,  Harold W. Kennel

发明人： Willy Rachmady ,  Van H. Le ,  Ravi Pillarisetty ,  Jack T. Kavalieros ,  Robert S. Chau ,  Harold W. Kennel

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/778 ,  H01L29/10 ,  H01L29/786 ,  H01L21/28 ,  H01L29/165 ,  H01L29/78 ,  B82Y10/00

CPC分类号： H01L29/1083 ,  B82Y10/00 ,  H01L21/28255 ,  H01L29/0603 ,  H01L29/0607 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7781 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78603 ,  H01L29/78684 ,  H01L29/78696

摘要： Semiconductor devices having germanium active layers with underlying diffusion barrier layers are described. For example, a semiconductor device includes a gate electrode stack disposed above a substrate. A germanium active layer is disposed above the substrate, underneath the gate electrode stack. A diffusion barrier layer is disposed above the substrate, below the germanium active layer. A junction leakage suppression layer is disposed above the substrate, below the diffusion barrier layer. Source and drain regions are disposed above the junction leakage suppression layer, on either side of the gate electrode stack.

公开(公告)号：US20160204037A1

公开(公告)日：2016-07-14

申请号：US14777736

申请日：2013-06-28

申请人： Niti Goel ,  Ravi Pillarisetty ,  Willy Rachmady ,  Jack T. Kavalieros ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Marko Radosavljevic ,  Matthew V. Metz ,  Niloy Mukherjee ,  Robert S. Chau

发明人： Niti Goel ,  Ravi Pillarisetty ,  Willy Rachmady ,  Jack T. Kavalieros ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Marko Radosavljevic ,  Matthew V. Metz ,  Niloy Mukherjee ,  Robert S. Chau

IPC分类号： H01L21/8238 ,  H01L21/762 ,  H01L21/02

CPC分类号： H01L21/823807 ,  H01L21/0245 ,  H01L21/02455 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/267 ,  H01L29/66795

摘要： Different n- and p-types of device fins are formed by epitaxially growing first epitaxial regions of a first type material from a substrate surface at a bottom of first trenches formed between shallow trench isolation (STI) regions. The STI regions and first trench heights are at least 1.5 times their width. The STI regions are etched away to expose the top surface of the substrate to form second trenches between the first epitaxial regions. A layer of a spacer material is formed in the second trenches on sidewalls of the first epitaxial regions. Second epitaxial regions of a second type material are grown from the substrate surface at a bottom of the second trenches between the first epitaxial regions. Pairs of n- and p-type fins can be formed from the first and second epitaxial regions. The fins are co-integrated and have reduced defects from material interface lattice mismatch.

摘要翻译： 通过从在浅沟槽隔离（STI）区域之间形成的第一沟槽的底部的衬底表面外延生长第一类型材料的第一外延区域，形成不同的n型和p型器件鳍。 STI区域和第​​一沟槽高度至少是其宽度的1.5倍。 蚀刻掉STI区域以暴露衬底的顶表面以在第一外延区域之间形成第二沟槽。 在第一外延区域的侧壁上的第二沟槽中形成间隔材料层。 在第二外延区域之间的第二沟槽的底部的衬底表面生长第二类型材料的第二外延区域。 可以从第一和第二外延区域形成正对和p型翅片对。 翅片是共同整合的，并且从材料界面晶格失配减少缺陷。

公开(公告)号：US08878363B2

公开(公告)日：2014-11-04

申请号：US12459254

申请日：2009-06-26

申请人： Gilbert Dewey ,  Niloy Mukherjee ,  Matthew Metz ,  Jack T. Kavalieros ,  Nancy M. Zelick ,  Robert S. Chau

发明人： Gilbert Dewey ,  Niloy Mukherjee ,  Matthew Metz ,  Jack T. Kavalieros ,  Nancy M. Zelick ,  Robert S. Chau

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L29/47 ,  H01L23/485 ,  H01L29/78 ,  H01L21/285 ,  H01L23/532 ,  H01L29/49 ,  H01L21/768 ,  H01L29/66

CPC分类号： H01L29/517 ,  H01B1/122 ,  H01L21/048 ,  H01L21/28525 ,  H01L21/324 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76841 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/53266 ,  H01L29/45 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/518 ,  H01L29/66643 ,  H01L29/7839 ,  H01L29/7853 ,  H01L31/022466 ,  H01L31/022475 ,  H01L33/0041 ,  H01L33/40 ,  H01L45/08 ,  H01L45/1206 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/145 ,  H01L51/102 ,  H01L51/105 ,  H01L51/441 ,  H01L51/442 ,  H01L51/5203 ,  H01L51/5234 ,  H01L2251/301 ,  H01L2251/303 ,  H01L2251/306 ,  H01L2251/308 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.

摘要翻译： 使用中间层来减少具有半导体衬底的半导体器件中的费米能级钉扎现象。 中间层可以是稀土氧化物。 中间层可以是离子半导体。 金属阻挡膜可以设置在中间层和金属耦合器之间。 中间层可以是金属阻挡膜和半导体基板的热处理组合。 形成中间层的方法可以包括对中间层进行分级。 计算系统包括中间层。

公开(公告)号：US20140091361A1

公开(公告)日：2014-04-03

申请号：US13631417

申请日：2012-09-28

申请人： Niti Goel ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Robert S. Chau ,  Willy Rachmady ,  Matthew V. Metz ,  Van H. Le ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Seung Hoon Sung

发明人： Niti Goel ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Robert S. Chau ,  Willy Rachmady ,  Matthew V. Metz ,  Van H. Le ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Seung Hoon Sung

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L27/092 ,  H01L21/0245 ,  H01L21/02538 ,  H01L21/823807 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78696

摘要： An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor.

公开(公告)号：US20130292698A1

公开(公告)日：2013-11-07

申请号：US13976840

申请日：2011-12-23

申请人： Han Wui Then ,  Marko Radosavljevic ,  Uday Shah ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Robert S. Chau

发明人： Han Wui Then ,  Marko Radosavljevic ,  Uday Shah ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Robert S. Chau

IPC分类号： H01L29/423 ,  H01L29/40

CPC分类号： H01L29/7787 ,  H01L21/02241 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/02258 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/268 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/31111 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/365 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/512 ,  H01L29/518 ,  H01L29/66462

摘要： III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack.