公开(公告)号：US07542297B2

公开(公告)日：2009-06-02

申请号：US11255061

申请日：2005-10-19

Applicant: James Douglas Wehrly, Jr. ,  Mark Wolfe ,  Paul Goodwin

Inventor： James Douglas Wehrly, Jr. ,  Mark Wolfe ,  Paul Goodwin

IPC: H05K1/00

CPC classification number: H05K1/189 ,  H01L25/0652 ,  H01L25/105 ,  H01L2924/0002 ,  H05K1/0203 ,  H05K1/118 ,  H05K1/181 ,  H05K3/0061 ,  H05K2201/056 ,  H05K2201/09445 ,  H05K2201/10159 ,  H05K2201/1056 ,  H05K2201/10734 ,  H05K2203/1572 ,  H01L2924/00

Abstract: A flexible circuitry is populated with integrated circuitry (ICs) disposed along one or both of its major sides. Contacts are distributed along the flexible circuitry to provide connection between the module and an application environment. A rigid substrate is configured to provide space on one side where the populated flex is disposed while in some embodiments, heat management or cooling structures are arranged on one side of the module to mitigate thermal accumulation in the module.

Abstract translation: 灵活的电路填充有沿其主要一侧或两侧设置的集成电路（IC）。 触点沿柔性电路分布，以提供模块与应用环境之间的连接。 刚性基板被配置为在其上布置有人造弹性体的一侧上提供空间，而在一些实施例中，热管理或冷却结构布置在模块的一侧以减轻模块中的热积聚。

公开(公告)号：US20090046431A1

公开(公告)日：2009-02-19

申请号：US12258189

申请日：2008-10-24

Applicant: James Douglas Wehrly, Jr. ,  James Wilder ,  Paul Goodwin ,  Mark Wolfe

Inventor： James Douglas Wehrly, Jr. ,  James Wilder ,  Paul Goodwin ,  Mark Wolfe

IPC: H05K7/20

CPC classification number: H05K1/189 ,  H05K1/0203 ,  H05K1/11 ,  H05K1/181 ,  H05K3/0061 ,  H05K2201/056 ,  H05K2201/09445 ,  H05K2201/10159 ,  H05K2201/1056 ,  H05K2201/10734 ,  H05K2203/1572

Abstract: Flexible circuitry is populated with integrated circuitry disposed along one or both of its major sides. Contacts distributed along the flexible circuitry provide connection between the module and an application environment. The circuit-populated flexible circuitry is disposed about an edge of a rigid substrate thus placing the integrated circuitry on one or both sides of the substrate with one or two layers of integrated circuitry on one or both sides of the substrate. The substrate form is preferably devised from thermally conductive materials and includes a high thermal conductivity core or area that is disposed proximal to higher thermal energy devices such as an AMB when the flex circuit is brought about the substrate. Other variations include thermally-conductive clips that grasp respective ICs on opposite sides of the module to further shunt heat from the ICs. Preferred extensions from the substrate body or substrate core encourage reduced thermal variations amongst the integrated circuits of the module.

Abstract translation: 灵活的电路填充有沿其主要侧面或其两侧设置的集成电路。 沿柔性电路分布的触点提供模块与应用环境之间的连接。 电路填充的柔性电路围绕刚性衬底的边缘设置，从而将集成电路放置在衬底的一侧或两侧，在衬底的一侧或两侧上具有一层或两层集成电路。 衬底形式优选地由导热材料设计，并且当柔性电路绕在衬底上时，包括设置在较高热能器件（例如AMB）附近的高导热性芯或区域。 其他变型包括将模块的相对侧上的相应IC夹持的导热夹子，以进一步从IC分流热量。 来自衬底主体或衬底芯的优选延伸部件促进模块集成电路之间的热变化减小。

公开(公告)号：US07468553B2

公开(公告)日：2008-12-23

申请号：US11682643

申请日：2007-03-06

Applicant: Leland Szewerenko ,  Paul Goodwin ,  James Douglas Wehrly, Jr.

Inventor： Leland Szewerenko ,  Paul Goodwin ,  James Douglas Wehrly, Jr.

IPC: H01L23/02

CPC classification number: H01L25/0657 ,  H01L24/48 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/4554

Abstract: The present invention provides a system and method for devising stackable assemblies that may be then stacked to create a stacked circuit module. One or more integrated circuit (IC) die are disposed on one or more sides of a redistribution substrate that is preferably flexible circuitry. In some preferred embodiments, the die and redistribution substrate are bonded together and wire-bond connected. Two or more stackable assemblies are interconnected through frame members to create low profile high density stacked circuit modules.

Abstract translation: 本发明提供了一种用于设计可堆叠组件的系统和方法，所述可堆叠组件可以被堆叠以产生堆叠电路模块。 一个或多个集成电路（IC）管芯设置在再分配衬底的一个或多个侧面上，其优选地是柔性电路。 在一些优选的实施方案中，将芯片和再分布衬底结合在一起并进行引线键合。 两个或多个可堆叠组件通过框架构件相互连接，以产生低轮廓的高密度堆叠电路模块。

公开(公告)号：US07310458B2

公开(公告)日：2007-12-18

申请号：US11258438

申请日：2005-10-25

Applicant: James Douglas Wehrly, Jr.

Inventor： James Douglas Wehrly, Jr.

IPC: G02B6/12 ,  H05K1/00 ,  H01L23/02

CPC classification number: H01L25/50 ,  H01L25/105 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2224/0401

Abstract: The present invention provides methods for constructing stacked circuit modules and precursor assemblies with flexible circuitry. Using the methods of the present invention, a single set of flexible circuitry whether articulated as one or two flex circuits may be employed with CSP devices of a variety of configurations either with or without form standards.

Abstract translation: 本发明提供用于构建具有柔性电路的堆叠电路模块和前体组件的方法。 使用本发明的方法，可以将具有铰接为一个或两个柔性电路的单组柔性电路与具有或不具有形式标准的各种配置的CSP装置一起使用。

公开(公告)号：US07259452B2

公开(公告)日：2007-08-21

申请号：US11248662

申请日：2005-10-11

Applicant: James Douglas Wehrly, Jr. ,  David Roper

Inventor： James Douglas Wehrly, Jr. ,  David Roper

IPC: H01L23/02

CPC classification number: H05K1/147 ,  H01L23/49827 ,  H01L23/5387 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/0002 ,  H05K1/141 ,  H05K1/189 ,  H05K3/3421 ,  H05K2201/049 ,  H05K2201/056 ,  H05K2201/09445 ,  H05K2201/10515 ,  H05K2201/10689 ,  H01L2924/00

Abstract: A system and method for electrically and thermally coupling adjacent IC packages to one another in a stacked configuration is provided. A flex circuit is inserted in part between ICs to be stacked and provides a connective field that provides plural contact areas that connect to respective leads of the ICs. Thus, the flex does not require discrete leads which must be individually aligned with the individual leads of the constituent ICs employed in the stack. The principle may be employed to aggregate two or more contact areas for respective connection to leads of constituent ICs but is most profitably employed with a continuous connective field that provides contact areas for many leads of the ICs.

Abstract translation: 提供了一种用于将堆叠配置中的相邻IC封装彼此电和热耦合的系统和方法。 将柔性电路部分地插入待堆叠的IC之间，并提供连接到IC的各个引线的多个接触区域的连接场。 因此，flex不需要离散引线，它们必须与堆叠中采用的构成IC的单个引线单独对准。 该原理可以用于聚合两个或更多个接触区域，以用于分别连接到构成IC的引线，但是对于提供IC的许多引线的接触面积的连续连接场最有利地使用。

公开(公告)号：US07180167B2

公开(公告)日：2007-02-20

申请号：US11011469

申请日：2004-12-14

Applicant: Julian Partridge ,  James W. Cady ,  James Wilder ,  David L. Roper ,  James Douglas Wehrly, Jr.

Inventor： Julian Partridge ,  James W. Cady ,  James Wilder ,  David L. Roper ,  James Douglas Wehrly, Jr.

IPC: H01L23/02

CPC classification number: H01L25/0657 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/5387 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/16237 ,  H01L2224/73253 ,  H01L2224/81011 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/3463 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2924/00

Abstract: The present invention provides a system and method that mounts integrated circuit devices onto substrates and a system and method for employing the method in stacked modules. The contact pads of a packaged integrated circuit device are substantially exposed. A solder paste that includes higher temperature solder paste alloy is applied to a substrate or to the integrated circuit device to be mounted. The integrated circuit device is positioned to contact the contacts of the substrate. Heat is applied to create high temperature joints between the contacts of the substrate and the integrated circuit device resulting in a device-substrate assembly with high temperature joints. The formed joints are less subject to re-melting in subsequent processing steps. The method may be employed in devising stacked module constructions such as those disclosed herein as preferred embodiments in accordance with the invention. Typically, the created joints are low in profile.

Abstract translation: 本发明提供了一种将集成电路器件安装到衬底上的系统和方法，以及用于将堆叠模块中采用该方法的系统和方法。 封装的集成电路器件的接触焊盘基本上露出。 将包括较高温度的焊膏合金的焊膏施加到要安装的基板或集成电路器件上。 集成电路器件定位成与衬底的触点接触。 施加热量以在基板的触点和集成电路装置之间形成高温接头，从而形成具有高温接头的装置 - 基板组件。 形成的接头在随后的加工步骤中较少受到再熔化。 该方法可以用于设计堆叠的模块结构，例如根据本发明的优选实施例中公开的那些。 通常，创建的关节的轮廓较低。

公开(公告)号：US07026708B2

公开(公告)日：2006-04-11

申请号：US10631886

申请日：2003-07-11

Applicant: James W. Cady ,  Julian Partridge ,  James Douglas Wehrly, Jr. ,  James Wilder ,  David L. Roper ,  Jeff Buchle

Inventor： James W. Cady ,  Julian Partridge ,  James Douglas Wehrly, Jr. ,  James Wilder ,  David L. Roper ,  Jeff Buchle

IPC: H01L23/488 ,  H05K1/14

CPC classification number: H05K1/141 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/5387 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/81801 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2924/01322 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  Y10T29/49126 ,  Y10T29/49144

Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into low profile modules that conserve PWB or other board surface area. Low profile contacts are created by any of a variety of methods and materials. A consolidated low profile contact structure and technique is provided for use in alternative embodiments of the present invention. Multiple numbers of CSPs may be stacked in accordance with the present invention. The CSPs employed in stacked modules devised in accordance with the present invention are connected with flex circuitry that exhibit one or two or more conductive layers.

Abstract translation: 本发明将芯片级封装集成电路（CSP）堆叠成保留PWB或其他板表面积的低轮廓模块。 薄型触点由各种方法和材料中的任何一种制成。 提供了一种合并的低轮廓接触结构和技术，用于本发明的替代实施例。 根据本发明可以堆叠多个CSP。 根据本发明设计的堆叠模块中采用的CSP与展现一个或两个或更多个导电层的柔性电路连接。

公开(公告)号：US06940729B2

公开(公告)日：2005-09-06

申请号：US10136890

申请日：2002-05-02

Applicant: James W. Cady ,  James Wilder ,  David L. Roper ,  Russell Rapport ,  James Douglas Wehrly, Jr. ,  Jeffrey Alan Buchle

Inventor： James W. Cady ,  James Wilder ,  David L. Roper ,  Russell Rapport ,  James Douglas Wehrly, Jr. ,  Jeffrey Alan Buchle

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H05K1/14 ,  H05K1/18 ,  H05K3/36 ,  H05K7/10 ,  H05K7/12

CPC classification number: H01L23/49816 ,  H01L23/3114 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/5387 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2924/00012

Abstract: The present invention stacks packaged integrated circuits into modules that conserve PWB or other board surface area. The invention provides techniques and structures for aggregating chip scale-packaged integrated circuits (CSPs) or leaded packages with other CSPs or with monolithic or stacked leaded packages into modules that conserve PWB or other board surface area. The present invention can be used to advantage with CSP or leaded packages of a variety of sizes and configurations ranging from larger packaged base elements having many dozens of contacts to smaller packages such as, for example, die-sized packages such as DSBGA. In a preferred embodiment devised in accordance with the present invention, a base element IC and a support element IC are aggregated through a flex circuit having at least two conductive layers that are patterned to selectively connect the two IC elements. A portion of the flex circuit connected to the support element is folded over the base element to dispose the support element above the base element while reducing the overall footprint occupied by the two ICs. The flex circuit connects the ICs and provides a thermal and electrical connection path between the module and an application environment such as a printed wiring board (PWB). The present invention may be employed to advantage in numerous configurations and combinations in modules provided for high-density memories, high capacity computing, or applications where small size is valued.

Abstract translation: 本发明将封装的集成电路堆叠成节省PWB或其他板表面积的模块。 本发明提供了用于将芯片级封装集成电路（CSP）或具有其他CSP的引线封装或者将单片或堆叠引线封装集成到节省PWB或其他板表面积的模块中的技术和结构。 本发明可以用于具有各种尺寸和配置的CSP或带引线的封装，其范围从具有许多触点的较大封装的基底元件到较小的封装，例如诸如管芯尺寸的封装（例如DSBGA）。 在根据本发明设计的优选实施例中，基体元件IC和支撑元件IC通过具有图案化以选择性地连接两个IC元件的至少两个导电层的柔性电路聚集。 连接到支撑元件的柔性电路的一部分折叠在基座元件上，以将支撑元件设置在基座元件上方，同时减少两个IC所占据的总占地面积。 柔性电路连接IC，并在模块和诸如印刷电路板（PWB）的应用环境之间提供热和电连接路径。 本发明可用于为高密度存储器，高容量计算或小尺寸的应用提供的模块中的多种配置和组合中的优点。

公开(公告)号：US06914324B2

公开(公告)日：2005-07-05

申请号：US10453398

申请日：2003-06-03

Applicant: Russell Rapport ,  James W. Cady ,  James Wilder ,  David L. Roper ,  James Douglas Wehrly, Jr. ,  Jeff Buchle

Inventor： Russell Rapport ,  James W. Cady ,  James Wilder ,  David L. Roper ,  James Douglas Wehrly, Jr. ,  Jeff Buchle

IPC: H01L21/44 ,  H01L23/31 ,  H01L23/498 ,  H01L23/50 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H05K1/14 ,  H05K1/18 ,  H05K3/36 ,  H01L23/02

CPC classification number: H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/50 ,  H01L23/5387 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01055 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2224/0401

Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard is disposed between the flex circuitry and the IC package over which a portion of the flex circuitry is laid. The form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance. In a preferred embodiment, a high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access. This favorably changes the impedance characteristics exhibited by a DIMM board populated with stacked modules. In a preferred embodiment, FET multiplexers for example, under logic control select particular data lines associated with particular levels of stacked modules populated upon a DIMM for connection to a controlling chip set in a memory expansion system.