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公开(公告)号：US10171099B2
公开(公告)日：2019-01-01
申请号：US15949479
申请日：2018-04-10
Applicant: Microchip Technology Incorporated
Inventor： Bryan Kris , Neil Deutscher
IPC: H03M1/34 , H03K5/131 , H03K5/14 , H03M1/10 , H03M1/38 , H03M1/00 , H03M1/18 , H03K5/00 , H03M1/50
Abstract: A differential digital delay line analog-to-digital converter (ADC) includes differential digital delay lines, a circuit including a set of delay elements included in the differential digital delay lines, and another circuit including another set of delay elements included in the differential digital delay lines. The first circuit is configured to generate data representing an analog to digital conversion of an input. The second circuit is configured to calibrate a source to the differential digital delay lines.
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公开(公告)号：US10120815B2
公开(公告)日：2018-11-06
申请号：US15184789
申请日：2016-06-16
Applicant: Microchip Technology Incorporated
Inventor： Michael Catherwood , David Mickey , Bryan Kris
Abstract: A single chip microcontroller has a master core and at least one slave core. The master core is clocked by a master system clock and the slave core is clocked by a slave system clock and wherein each core is associated with a plurality of peripheral devices to form a master microcontroller and a slave microcontroller, respectively. A communication interface is provided between the master microcontroller and the slave microcontroller, wherein the communication interface has a plurality of configurable directional data registers coupled with a flow control logic which is configurable to assign a direction to each of the plurality of configurable data registers.
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公开(公告)号：US20180198461A1
公开(公告)日：2018-07-12
申请号：US15915796
申请日：2018-03-08
Applicant: Microchip Technology Incorporated
Inventor： Bryan Kris , Neil Deutscher , Thomas S. Spohrer
CPC classification number: H03M1/34 , H03K5/131 , H03K5/14 , H03K2005/00058 , H03M1/007 , H03M1/1009 , H03M1/1028 , H03M1/1057 , H03M1/1071 , H03M1/18 , H03M1/38 , H03M1/502
Abstract: Embodiments of the present disclosure include a differential digital delay line analog-to-digital converter (ADC), comprising differential digital delay lines including series coupled delay cells, wherein a delay time of a first delay line is controlled by a first input of the ADC and a delay time of a second delay line is controlled by a second input of the ADC. The ADC includes a pair of bypass multiplexers coupled at a predefined node location in the series coupled delay cells, latches each coupled with the series coupled delay cells, a converter circuit coupled with the plurality of latches configured to convert data from the latches into an output value of the ADC, and logic circuits configured to select data from the series coupled delay cells to the latches depending on a selected resolution of the differential digital delay line analog-to-digital converter.
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公开(公告)号：US10002103B2
公开(公告)日：2018-06-19
申请号：US15065027
申请日：2016-03-09
Applicant: Microchip Technology Incorporated
Inventor： Bryan Kris , Igor Wojewoda , Alex Dumais , Mike Catherwood , Brian Fall , Jason Tollefson , Calum Wilke , Dave Mickey , Thomas Spohrer , Jim Pepping , Vincent Sheard
IPC: G06F13/00 , G06F3/00 , G06F13/42 , G06F13/364 , G06F13/16 , G06F13/38 , G06F15/167 , G06F1/22
CPC classification number: G06F13/4282 , G06F1/22 , G06F13/1673 , G06F13/364 , G06F13/385 , G06F15/167 , Y02D10/14 , Y02D10/151
Abstract: A microcontroller device has a housing with a plurality of external pins a first microcontroller with a first central processing unit (CPU), a first system bus coupled with the first CPU, first memory coupled with the first system bus, and a first plurality of peripheral devices coupled with the first system bus, and a second microcontroller with a second central processing unit (CPU), a second system bus coupled with the second CPU, second memory coupled with the second system bus, and a second plurality of peripheral devices coupled with the second system bus, wherein first and second microcontroller communicate only via a dedicated interface.
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公开(公告)号：US10002102B2
公开(公告)日：2018-06-19
申请号：US15064964
申请日：2016-03-09
Applicant: Microchip Technology Incorporated
Inventor： Bryan Kris , Igor Wojewoda , Alex Dumais , Mike Catherwood , Brian Fall , Jason Tollefson , Calum Wilke , Dave Mickey , Thomas Spohrer
CPC classification number: G06F13/4282 , G06F13/1673 , G06F13/364 , G06F13/385 , G06F15/7807 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
Abstract: A microcontroller device has a housing with a plurality of external pins having a plurality of input/output pins, a first microcontroller with a first central processing unit (CPU), a first system bus coupled with the first CPU, first memory coupled with the first system bus, and a first plurality of peripheral devices coupled with the first system bus, a second microcontroller with a second central processing unit (CPU), a second system bus coupled with the second CPU, second memory coupled with the second system bus, and a second plurality of peripheral devices coupled with the second system bus, and a pad ownership multiplexer unit being controllable to assign control of the input/output pins to either the first microcontroller or the second microcontroller, wherein the number of external pins is less than the sum of a data buswidth of the first and second microcontroller.
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Patent Agency Ranking
46.发明授权公开(公告)号：US09906235B2
公开(公告)日：2018-02-27
申请号：US15484987
申请日：2017-04-11
Applicant: Microchip Technology Incorporated
Inventor： Bryan Kris
CPC classification number: H03M1/34 , H03K5/131 , H03K5/14 , H03K2005/00058 , H03M1/007 , H03M1/1009 , H03M1/1028 , H03M1/1057 , H03M1/1071 , H03M1/18 , H03M1/38 , H03M1/502
Abstract: Embodiments of the present disclosure include a microcontroller with a processor core, memory, and a plurality of peripheral devices including a differential digital delay line analog-to-digital converter (ADC). The ADC includes differential digital delay lines and circuit comprising a set of delay elements included in the differential digital delay lines configured to generate data representing an analog to digital conversion of an input. The microcontroller also includes a digital comparator coupled with an output of the ADC and an associated register, wherein at least one output of the digital comparator is configured to directly control another peripheral of the plurality of peripherals.
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公开(公告)号：US20180026648A1
公开(公告)日：2018-01-25
申请号：US15652710
申请日：2017-07-18
Applicant: Microchip Technology Incorporated
Inventor： Bryan Kris , Jim Bartling , Neil Deutscher
CPC classification number: H03M1/502 , H03K5/14 , H03K5/24 , H03M1/1205
Abstract: Embodiments of the present disclosure include voltage comparators. The voltage comparators may include a first input configured to receive a first analog voltage, a second input configured to receive a second analog voltage, a first digital delay line configured to propagate the first analog voltage through a first delay circuit and the second analog voltage through a second circuit, and an output circuit configured to provide a comparator output based upon whether values representing the first analog voltage or the second analog voltage propagated faster through the first digital delay line. The comparator output may be configured to identify whether the first analog voltage or the second analog voltage is greater.
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公开(公告)号：US20180026596A1
公开(公告)日：2018-01-25
申请号：US15723142
申请日：2017-10-02
Applicant: Microchip Technology Incorporated
Inventor： Bryan Kris , James E. Bartling
CPC classification number: H03G1/0088 , H03F3/45475 , H03F2200/321 , H03F2203/45048 , H03F2203/45528 , H03F2203/45534 , H03F2203/45616 , H03F2203/45728 , H03G3/001
Abstract: An integrated circuit amplifier configurable to be either a programmable gain amplifier or an operational amplifier comprises two output blocks, one output block is optimized for programmable gain amplifier operation, and the other output block is optimized for operational amplifier applications. A common single input stage, input offset calibration and bias generation circuits are used with either amplifier configuration. Thus duplication of the input stage, offset calibration and bias generation circuits are eliminated while still selectably providing for either a programmable gain amplifier or operational amplifier configuration.
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49.发明申请公开(公告)号：US20170294917A1
公开(公告)日：2017-10-12
申请号：US15484987
申请日：2017-04-11
Applicant: Microchip Technology Incorporated
Inventor： Bryan Kris
CPC classification number: H03M1/34 , H03K5/131 , H03K5/14 , H03K2005/00058 , H03M1/007 , H03M1/1009 , H03M1/1028 , H03M1/1057 , H03M1/1071 , H03M1/18 , H03M1/38 , H03M1/502
Abstract: Embodiments of the present disclosure include a microcontroller with a processor core, memory, and a plurality of peripheral devices including a differential digital delay line analog-to-digital converter (ADC). The ADC includes differential digital delay lines and circuit comprising a set of delay elements included in the differential digital delay lines configured to generate data representing an analog to digital conversion of an input. The microcontroller also includes a digital comparator coupled with an output of the ADC and an associated register, wherein at least one output of the digital comparator is configured to directly control another peripheral of the plurality of peripherals.
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公开(公告)号：US09780748B2
公开(公告)日：2017-10-03
申请号：US14863779
申请日：2015-09-24
Applicant: Microchip Technology Incorporated
Inventor： Bryan Kris , James E. Bartling
CPC classification number: H03G1/0088 , H03F3/45475 , H03F2200/321 , H03F2203/45048 , H03F2203/45528 , H03F2203/45534 , H03F2203/45616 , H03F2203/45728 , H03G3/001
Abstract: An integrated circuit amplifier configurable to be either a programmable gain amplifier or an operational amplifier comprises two output blocks, one output block is optimized for programmable gain amplifier operation, and the other output block is optimized for operational amplifier applications. A common single input stage, input offset calibration and bias generation circuits are used with either amplifier configuration. Thus duplication of the input stage, offset calibration and bias generation circuits are eliminated while still selectably providing for either a programmable gain amplifier or operational amplifier configuration.
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