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    Single Spacer Process for Multiplying Pitch by a Factor Greater Than Two and Related Intermediate IC Structures
    41.
    发明申请
    Single Spacer Process for Multiplying Pitch by a Factor Greater Than Two and Related Intermediate IC Structures 有权
    单个间隔过程乘以一个大于两个因子和相关的中间IC结构

    公开(公告)号：US20150054168A1

    公开(公告)日：2015-02-26

    申请号：US14528999

    申请日：2014-10-30

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： David H. Wells ,  Mirzafer K. Abatchev

    IPC: H01L23/538 ,  H01L27/105

    CPC classification number: H01L23/5386 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/1052 ,  H01L2924/0002 ,  Y10S438/942 ,  Y10S438/946 ,  Y10S438/947 ,  H01L2924/00

    Abstract: Single spacer processes for multiplying pitch by a factor greater than two are provided. In one embodiment, n, where n≧2, tiers of stacked mandrels are formed over a substrate, each of the n tiers comprising a plurality of mandrels substantially parallel to one another. Mandrels at tier n are over and parallel to mandrels at tier n−1, and the distance between adjoining mandrels at tier n is greater than the distance between adjoining mandrels at tier n−1. Spacers are simultaneously formed on sidewalls of the mandrels. Exposed portions of the mandrels are etched away and a pattern of lines defined by the spacers is transferred to the substrate.

    Abstract translation: 提供了用于将音调乘以大于2的因子的单间隔物处理。 在一个实施例中，n，其中n≥2，在衬底上形成层叠的心轴层，n层​​中的每一层包括基本上彼此平行的多个心轴。 层n上的心轴结束并平行于n-1层的心轴，层n的相邻心轴之间的距离大于n-1层相邻心轴之间的距离。 间隔件同时形成在心轴的侧壁上。 蚀刻掉心轴的裸露部分，并且由间隔物限定的线的图案被转移到基底。

    RESISTIVE MEMORY AND METHODS OF PROCESSING RESISTIVE MEMORY
    42.
    发明申请
    RESISTIVE MEMORY AND METHODS OF PROCESSING RESISTIVE MEMORY 有权
    电阻记忆和处理电阻记忆的方法

    公开(公告)号：US20140326941A1

    公开(公告)日：2014-11-06

    申请号：US14302792

    申请日：2014-06-12

    Applicant: Micron Technology, Inc.

    Inventor： David H. Wells

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/126 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/144 ,  H01L45/16

    Abstract: Resistive memory and methods of processing resistive memory are described herein. One or more method embodiments of processing resistive memory include forming a resistive memory cell material on an electrode having an access device contact, and forming a heater electrode on the resistive memory cell material after forming the resistive memory cell material on the electrode such that the heater electrode is self-aligned to the resistive memory cell material.

    Abstract translation: 本文描述了电阻存储器和处理电阻性存储器的方法。 处理电阻性存储器的一个或多个方法实施例包括在具有存取装置接触的电极上形成电阻性存储单元材料，以及在电阻上形成电阻式存储单元材料之后，在电阻式存储单元材料上形成加热器电极，使得加热器 电极与电阻式存储单元材料自对准。

    Methods of Forming Metal Silicide-Comprising Material and Methods of Forming Metal Silicide-Comprising Contacts
    43.
    发明申请
    Methods of Forming Metal Silicide-Comprising Material and Methods of Forming Metal Silicide-Comprising Contacts 有权
    形成金属硅化物的方法及其形成金属硅化物的方法

    公开(公告)号：US20140134816A1

    公开(公告)日：2014-05-15

    申请号：US14157192

    申请日：2014-01-16

    Applicant: Micron Technology, Inc.

    Inventor： David H. Wells ,  John Mark Meldrim ,  Rita J. Klein

    IPC: H01L21/28 ,  H01L21/283

    CPC classification number: H01L21/28097 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/32134 ,  H01L21/32139

    Abstract: A method of forming metal silicide-comprising material includes forming a substrate which includes a first stack having second metal over first metal over silicon and a second stack having second metal over silicon. The first and second metals are of different compositions. The substrate is subjected to conditions which react the second metal with the silicon in the second stack to form metal silicide-comprising material from the second stack. The first metal between the second metal and the silicon in the first stack precludes formation of a silicide comprising the second metal and silicon from the first stack. After forming the metal silicide-comprising material, the first metal, the second metal and the metal silicide-comprising material are subjected to an etching chemistry that etches at least some remaining of the first and second metals from the substrate selectively relative to the metal silicide-comprising material.

    Abstract translation: 一种形成含金属硅化物的材料的方法包括形成衬底，该衬底包括具有超过硅的第一金属上的第二金属的第一堆叠和在硅上的第二金属的第二叠层。 第一和第二种金属具有不同的组成。 基板经受使第二金属与第二堆叠中的硅反应以形成来自第二堆叠的含金属硅化物的材料的条件。 第一堆叠中的第二金属和硅之间的第一金属阻止从第一堆叠形成包括第二金属和硅的硅化物。 在形成含金属硅化物的材料之后，对第一金属，第二金属和含金属硅化物的材料进行蚀刻化学，从而选择性地相对于金属硅化物从衬底中蚀刻至少一些剩余的第一和第二金属 令人惊奇的材料。

    SEMICONDUCTOR STRUCTURES AND DEVICES AND METHODS OF FORMING THE SAME
    44.
    发明申请
    SEMICONDUCTOR STRUCTURES AND DEVICES AND METHODS OF FORMING THE SAME 有权
    半导体结构和器件及其形成方法

    公开(公告)号：US20140021577A1

    公开(公告)日：2014-01-23

    申请号：US14034014

    申请日：2013-09-23

    Applicant: Micron Technology, Inc.

    Inventor： David H. Wells ,  Gurtej S. Sandhu

    IPC: H01L29/06 ,  H01L21/761

    CPC classification number: H01L23/528 ,  H01L21/2236 ,  H01L21/30604 ,  H01L21/32051 ,  H01L21/32053 ,  H01L21/32055 ,  H01L21/743 ,  H01L21/761 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/84 ,  H01L23/53257 ,  H01L23/53261 ,  H01L23/53271 ,  H01L27/1027 ,  H01L27/1203 ,  H01L27/2472 ,  H01L29/04 ,  H01L29/06 ,  H01L29/167 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/16

    Abstract: Methods of forming semiconductor structures that include bodies of a semiconductor material disposed between rails of a dielectric material are disclosed. Such methods may include filling a plurality of trenches in a substrate with a dielectric material and removing portions of the substrate between the dielectric material to form a plurality of openings. In some embodiments, portions of the substrate may be undercut to form a continuous void underlying the bodies and the continuous void may be filled with a conductive material. In other embodiments, portions of the substrate exposed within the openings may be converted to a silicide material to form a conductive material under the bodies. For example, the conductive material may be used as a conductive line to electrically interconnect memory device components. Semiconductor structures and devices formed by such methods are also disclosed.

    Abstract translation: 公开了形成半导体结构的方法，该半导体结构包括设置在电介质材料的轨道之间的半导体材料的主体。 这样的方法可以包括用电介质材料填充衬底中的多个沟槽并且去除介电材料之间的衬底的部分以形成多个开口。 在一些实施例中，衬底的部分可以被底切以在主体下面形成连续的空隙，并且连续的空隙可以用导电材料填充。 在其他实施例中，暴露在开口内的基板的部分可以转化为硅化物材料，以在主体下面形成导电材料。 例如，导电材料可以用作导电线以电连接存储器件部件。 还公开了通过这些方法形成的半导体结构和器件。

    MEMORY DEVICE INCLUDING DIFFERENT DIELECTRIC STRUCTURES BETWEEN BLOCKS
    46.
    发明申请
    MEMORY DEVICE INCLUDING DIFFERENT DIELECTRIC STRUCTURES BETWEEN BLOCKS 有权

    公开(公告)号：US20250142831A1

    公开(公告)日：2025-05-01

    申请号：US19004725

    申请日：2024-12-30

    Applicant: Micron Technology, Inc.

    Inventor： Paolo Tessariol ,  David H. Wells ,  Umberto Maria Meotto

    IPC: H10B43/50 ,  H01L23/522 ,  H01L23/528 ,  H10B41/27 ,  H10B41/50 ,  H10B43/27

    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes levels of conductive materials interleaved with levels of dielectric materials; memory cell strings including respective pillars extending through the levels of conductive materials and the levels of dielectric materials; a first dielectric structure formed in a first slit through the levels of conductive materials and the levels of dielectric materials; a second dielectric structure formed in a second slit through the levels of conductive materials and the levels of dielectric materials; the first dielectric structure and the second dielectric structure separating the levels of conductive materials, the levels of dielectric materials, and the pillars into separate portions, and the first and second dielectric structures including different widths.

    Dense piers for three-dimensional memory arrays
    48.
    发明授权
    Dense piers for three-dimensional memory arrays 有权

    公开(公告)号：US12245438B2

    公开(公告)日：2025-03-04

    申请号：US17656287

    申请日：2022-03-24

    Applicant: Micron Technology, Inc.

    Inventor： Stephen W. Russell ,  Enrico Varesi ,  David H. Wells ,  Paolo Fantini ,  Lorenzo Fratin

    IPC: H01L27/24 ,  H01L45/00 ,  H10B63/00 ,  H10N70/00

    Abstract: Methods, systems, and devices for dense piers for three-dimensional memory arrays are described. In some examples, a memory device may include pier structures formed in contact with features formed from alternating layers of materials deposited over a substrate. For example, a memory device may include alternating layers of a first material and a second material. In some examples, the alternating layers may be formed into a pair of interleaved comb structures. Pier structures may be formed in contact with the cross sectional patterns, and may provide mechanical support of cross-sectional pattern of the remaining material. In some examples, the piers may further act as a separator between memory cells or other features of the memory device. For example, the piers may extend into at least a portion of the interleaved comb structures, and may accordingly act as barriers during subsequent depositions of materials.

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