公开(公告)号：US10522395B1

公开(公告)日：2019-12-31

申请号：US16107407

申请日：2018-08-21

Applicant: Micron Technology, Inc.

Inventor： Scott L. Light ,  Richard J. Hill

IPC: H01L23/52 ,  H01L21/768 ,  H01L21/033 ,  H01L23/522 ,  H01L23/528

Abstract: A metal pattern comprising interconnected small metal segments, medium metal segments, and large metal segments. At least one of the small metal segments comprises a pitch of less than about 45 nm and the small metal segments, medium metal segments, and large metal segments are separated from one another by variable spacing. Semiconductor devices comprising initial metallizations, systems comprising the metal pattern, and methods of forming a pattern are also disclosed.

公开(公告)号：US20190189515A1

公开(公告)日：2019-06-20

申请号：US15843493

申请日：2017-12-15

Applicant: Micron Technology, Inc.

Inventor： David K. Hwang ,  John A. Smythe ,  Haitao Liu ,  Richard J. Hill ,  Deepak Chandra Pandey

IPC: H01L21/8239 ,  H01L21/8229 ,  H01L21/8234 ,  H01L29/10 ,  G11C11/40

CPC classification number: H01L21/8239 ,  G11C11/40 ,  G11C2211/4016 ,  H01L21/8229 ,  H01L21/823437 ,  H01L21/823462 ,  H01L29/105

Abstract: An embodiment of the invention comprises a method of forming a transistor comprising forming a gate construction having an elevationally-outermost surface of conductive gate material that is lower than an elevationally-outer surface of semiconductor material that is aside and above both sides of the gate construction. Tops of the semiconductor material and the conductive gate material are covered with masking material, two pairs of two opposing sidewall surfaces of the semiconductor material are laterally exposed above both of the sides of the gate construction. After the covering, the semiconductor material that is above both of the sides of the gate construction is subjected to monolayer doping through each of the laterally-exposed two opposing sidewall surfaces of each of the two pairs and forming there-from doped source/drain regions above both of the sides of the gate construction.

公开(公告)号：US20180219021A1

公开(公告)日：2018-08-02

申请号：US15422335

申请日：2017-02-01

Applicant: Micron Technology, Inc.

Inventor： David Daycock ,  Richard J. Hill ,  Christopher Larsen ,  Woohee Kim ,  Justin B. Dorhout ,  Brett D. Lowe ,  John D. Hopkins ,  Qian Tao ,  Barbara L. Casey

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/10 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L27/1157 ,  H01L29/1037 ,  H01L29/4234

Abstract: Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels and not along the insulative levels. The charge-trapping material is spaced from the control gate regions by charge-blocking material. Channel material extends vertically along the stack and is laterally spaced from the charge-trapping material by dielectric material. Some embodiments include methods of forming NAND memory arrays.

公开(公告)号：US20250046711A1

公开(公告)日：2025-02-06

申请号：US18782634

申请日：2024-07-24

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Richard J. Hill

IPC: H01L23/528 ,  G11C16/04 ,  H01L23/00 ,  H01L23/522 ,  H01L25/065 ,  H10B41/20 ,  H10B41/35 ,  H10B43/20 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor device assembly including a substrate; a plurality of functional devices disposed above the substrate; and a memory device disposed above the plurality of functional devices, the memory device including one or more memory arrays, a plurality of first vertical electrical connectors having a first diameter and extending vertically, and a plurality of second vertical electrical connectors having a second diameter and extending vertically, wherein the second diameter is greater than the first diameter.

公开(公告)号：US20240099007A1

公开(公告)日：2024-03-21

申请号：US18525652

申请日：2023-11-30

Applicant: Micron Technology, Inc.

Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Matthew J. King ,  Sidhartha Gupta ,  Paolo Tessariol ,  Kunal Shrotri ,  Kye Hyun Baek ,  Kyle A. Ritter ,  Shuji Tanaka ,  Umberto Maria Meotto ,  Richard J. Hill ,  Matthew Holland

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: A microelectronic device comprises a stack structure comprising a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, the stack structure divided into block structures separated from one another by slot structures, strings of memory cells vertically extending through the block structures of the stack structure, the strings of memory cells individually comprising a channel material vertically extending through the stack structure, an additional stack structure vertically overlying the stack structure and comprising a vertical sequence of additional conductive structures and additional insulative structures arranged in additional tiers, first pillars extending through the additional stack structure and vertically overlying the strings of memory cells, each of the first pillars horizontally offset from a center of a corresponding string of memory cells, second pillars extending through the additional stack structure and vertically overlying the strings of memory cells, and additional slot structures comprising a dielectric material extending through at least a portion of the additional stack structure and sub-dividing each of the block structures into sub-block structures, the additional slot structures horizontally neighboring the first pillars. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US20240071918A1

公开(公告)日：2024-02-29

申请号：US17822421

申请日：2022-08-25

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Sidhartha Gupta ,  Indra V. Chary ,  Richard J. Hill ,  Umberto Maria Meotto

IPC: H01L23/528 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/5283 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582

Abstract: A microelectronic device includes a stack structure having tiers each including conductive material vertically neighboring insulative material and conductive contact structures. The stack structure is divided into blocks horizontally extending in parallel in a first direction and separated from one another in a second direction orthogonal to the first direction by insulative slot structures. At least one of the blocks includes a lower stadium structure having steps including edges of some of the tiers, and an upper stadium structure vertically overlying the lower stadium structure and having additional steps including edges of some other of the tiers vertically overlying the some of the tiers. The additional steps have greater tread widths in the first direction than the steps. Conductive contact structures are in contact with the additional steps of the upper stadium structure of the at least one of the blocks. Memory devices and electronic systems are also described.

公开(公告)号：US20230320085A1

公开(公告)日：2023-10-05

申请号：US17710262

申请日：2022-03-31

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Richard J. Hill

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11521 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11565

CPC classification number: H01L27/11556 ,  H01L27/11582 ,  H01L27/11521 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11565

Abstract: A memory array comprising strings of memory cells comprises a vertical stack comprising vertically-alternating insulative tiers and conductive tiers directly above a conductor tier. Channel-material-string constructions of memory-cell strings extend through the insulative and conductive tiers. The channel material of the channel-material-string constructions directly electrically couples with conductor material of the conductor tier. The vertical stack comprising a memory-cell region comprises memory cells. Individual of the insulative tiers in the memory-cell region laterally-outward of the channel-material-string constructions have at least a majority of their insulative matter being void space. The vertical stack comprises an upper region directly above the memory-cell region. The upper region comprises at least two of the conductive tiers and that comprise upper select gates Individual of the insulative tiers in the upper region laterally-outward of the channel-material-string constructions have at least a majority of their insulative matter being solid. Other embodiments, including method, are disclosed.

公开(公告)号：US20230262981A1

公开(公告)日：2023-08-17

申请号：US18138350

申请日：2023-04-24

Applicant: Micron Technology, Inc.

Inventor： Byeung Chul Kim ,  Francois H. Fabreguette ,  Richard J. Hill ,  Purnima Narayanan ,  Shyam Surthi

IPC: H10B43/27 ,  G11C16/08 ,  H01L21/02 ,  H10B43/35

CPC classification number: H10B43/27 ,  G11C16/08 ,  H01L21/0214 ,  H10B43/35

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels have conductive terminal ends within control gate regions. The control gate regions are vertically spaced from one another by first insulative regions which include first insulative material. Charge-storage material is laterally outward of the conductive terminal ends, and is configured as segments. The segments of the charge-storage material are arranged one atop another and are vertically spaced from one another by second insulative regions which include second insulative material. The second insulative material has a different dielectric constant than the first insulative material. Charge-tunneling material extends vertically along the stack, and is adjacent to the segments of the charge-trapping material. Channel material extends vertically along the stack, and is adjacent to the charge-tunneling material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11631697B2

公开(公告)日：2023-04-18

申请号：US17672659

申请日：2022-02-15

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Byeung Chul Kim ,  Richard J. Hill ,  Francois H. Fabreguette ,  Gurtej S. Sandhu

IPC: H01L27/11582 ,  G11C5/06 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157

Abstract: Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. A channel material extends vertically along the stack. The channel material includes a semiconductor composition and has first segments alternating with second segments. The first segments are adjacent the wordline levels and the second segments are adjacent the insulative levels. The first segments have a first dopant distribution and the second segments have a second dopant distribution which is different from the first dopant distribution. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11563031B2

公开(公告)日：2023-01-24

申请号：US17369630

申请日：2021-07-07

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Richard J. Hill

IPC: H01L27/11582 ,  H01L21/768 ,  H01L45/00

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and distal regions proximate the control gate regions. The control gate regions have front surfaces, top surfaces and bottom surfaces. The top and bottoms surfaces extend back from the front surfaces. High-k dielectric material is along the control gate regions. The high-k dielectric material has first regions along the top and bottom surfaces, and has second regions along the front surfaces. The first regions are thicker than the second regions. Charge-blocking material is adjacent to the second regions of the high-k dielectric material. Charge-storage material is adjacent to the charge-blocking material. Gate-dielectric material is adjacent to the charge-storage material. Channel material is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.