公开(公告)号：US07128821B2

公开(公告)日：2006-10-31

申请号：US10761477

申请日：2004-01-20

申请人： Shih-Ho Lin ,  Chung-Chang Chen ,  Kei-Wei Chen ,  Shih-Tzung Chang ,  Chao-Lung Chen ,  Po-Jen Shih ,  Yu-Ku Lin ,  Ying-Lang Wang

发明人： Shih-Ho Lin ,  Chung-Chang Chen ,  Kei-Wei Chen ,  Shih-Tzung Chang ,  Chao-Lung Chen ,  Po-Jen Shih ,  Yu-Ku Lin ,  Ying-Lang Wang

IPC分类号： C25D5/34 ,  C25F1/00

CPC分类号： H01L21/76843 ,  B24B37/042 ,  B24B37/046 ,  C25D3/38 ,  C25D5/18 ,  C25D7/123 ,  C25F3/02 ,  H01L21/02068 ,  H01L21/32115 ,  H01L21/76865 ,  H01L21/76873

摘要： An electropolishing method for removing potential device-contaminating particles from a wafer, is disclosed. The method includes immersing the wafer in an electropolishing electrolyte solution and removing defects and particles from the wafer by rotational friction between the wafer and the electrolyte solution in combination with electrolysis. The method is effective in removing particles from via openings of all sizes, including via openings having a width smaller than about 0.2 μm.

摘要翻译： 公开了一种用于从晶片去除潜在的器件污染颗粒的电抛光方法。 该方法包括将晶片浸入电解抛光电解质溶液中，并通过晶片和电解质溶液之间的旋转摩擦与电解结合从晶片去除缺陷和颗粒。 该方法有效地从各种尺寸的通孔开口去除颗粒，包括宽度小于约0.2μm的通孔。

公开(公告)号：US20060055928A1

公开(公告)日：2006-03-16

申请号：US10942554

申请日：2004-09-15

申请人： Shih-Tzung Chang ,  Yu-Ku Lin ,  Shih-Ho Lin ,  Kei-Wei Chen ,  Ting-Chun Wang ,  Ching-Hwan Su ,  Ying-Lang Wang

发明人： Shih-Tzung Chang ,  Yu-Ku Lin ,  Shih-Ho Lin ,  Kei-Wei Chen ,  Ting-Chun Wang ,  Ching-Hwan Su ,  Ying-Lang Wang

IPC分类号： G01B11/00

CPC分类号： H01L22/34 ,  G01B21/042

摘要： A novel test device and method for calibrating the alignment of a laser beam emitted from a laser metrology tool with respect to a target area on a substrate. The test device includes a laser-sensitive material having a calibration pattern that includes a target point. When the tool is properly adjusted, the laser beam strikes the target point and is released to production. If the laser beam misses the target point, the tool is re-adjusted and re-tested until the laser beam strikes the target point.

摘要翻译： 一种用于校准从激光计量工具发射的激光束相对于衬底上的目标区域的对准的新型测试装置和方法。 测试装置包括具有包括目标点的校准图案的激光敏感材料。 当工具被正确调整时，激光束撞击目标点并释放到生产中。 如果激光束错过目标点，则重新调整工具并重新测试直到激光束撞击目标点。

公开(公告)号：US20050236181A1

公开(公告)日：2005-10-27

申请号：US10917543

申请日：2004-08-12

申请人： Kei-Wei Chen ,  Shih-Ho Lin ,  Chun-Chang Chen ,  Ching-Hwan Su ,  Yu-Ku Lin ,  Ying-Lang Wang ,  De-Dui Liao ,  Meng-Chao Tzeng

发明人： Kei-Wei Chen ,  Shih-Ho Lin ,  Chun-Chang Chen ,  Ching-Hwan Su ,  Yu-Ku Lin ,  Ying-Lang Wang ,  De-Dui Liao ,  Meng-Chao Tzeng

IPC分类号： H01L21/768 ,  H01L23/522 ,  H05K1/03 ,  H05K1/09 ,  H05K1/11

CPC分类号： H01L21/76816 ,  H01L21/76807 ,  H01L23/5226 ,  H01L2924/0002 ,  Y10T29/49165 ,  H01L2924/00

摘要： A method for preventing the formation of voids and contaminants in vias during the fabrication of a metal interconnect structure such as a dual damascene structure is disclosed. The method includes providing a substrate; providing a dielectric layer having trench openings and via openings on the substrate, wherein the ratio of the sum of the areas of the trench openings to the sum of the areas of the via openings is between 1 and 300; wherein the via opening bottom has a width of less than about 25 μm; and electroplating a metal in the trench openings and via openings. An interconnect structure having at least one void-free via is further disclosed.

摘要翻译： 公开了一种用于在金属互连结构例如双镶嵌结构的制造期间防止在通孔中形成空隙和污染物的方法。 该方法包括提供基板; 在衬底上提供具有沟槽开口和通孔开口的电介质层，其中沟槽开口的面积之和与通路孔的面积之和的比值在1和300之间; 其中所述通孔开口底部具有小于约25μm的宽度; 以及在沟槽开口和通孔中电镀金属。 还公开了具有至少一个无空隙通孔的互连结构。

公开(公告)号：US20050124151A1

公开(公告)日：2005-06-09

申请号：US10728215

申请日：2003-12-04

申请人： Yi-Lung Cheng ,  Ren-Haur Liu ,  Cheng-Hsiung Liu ,  Ying-Lang Wang ,  Hway-Chi Lin ,  Chien-Ming Chiu

发明人： Yi-Lung Cheng ,  Ren-Haur Liu ,  Cheng-Hsiung Liu ,  Ying-Lang Wang ,  Hway-Chi Lin ,  Chien-Ming Chiu

IPC分类号： C23C16/40 ,  H01L21/316 ,  H01L21/768 ,  H01L21/4763 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/02126 ,  C23C16/401 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76819

摘要： A method is disclosed for depositing a Black Diamond layer in a CVD chamber. Trimethylsilane, O2, and Ar are flowed into the chamber at 300° C. to 400° C. with an O2:Ar:trimethylsilane flow rate ratio that is preferably 1:1.5:6. The resulting low k dielectric layer is formed with a higher deposition rate than when Ar is omitted and has a k value of about 3 that increases only slightly in O2 plasma. A higher density, hardness, and tensile strength are achieved in the Black Diamond layer when Ar is included in the deposition process. The addition of Ar in the deposition maintains film thickness uniformity below 2% for a longer period so that PM cleaning operations are less frequent and affords a lower fluorocarbon plasma etch rate to enable improved trench depth control in a damascene scheme. A lower leakage current and higher breakdown voltage in achieved in the resulting metal interconnect.

摘要翻译： 公开了一种用于在CVD室中沉积黑金刚石层的方法。 三甲基硅烷O 2和Ar在300℃至400℃下以0:2:Ar:三甲基硅烷流速比流入室中，优选 1：1.5：6。 形成的低k电介质层的沉积速率高于省略Ar时的沉积速率，并且具有约3的K值仅在O 2等离子体中略微增加。 当在沉积过程中包含Ar时，在黑色金刚石层中获得较高的密度，硬度和拉伸强度。 沉积中Ar的添加将膜厚度均匀性维持在2％以下更长的时间，以便PM清洁操作较不频繁，并提供较低的氟碳等离子体蚀刻速率，从而能够改进镶嵌方案中的沟槽深度控制。 在所得到的金属互连中实现较低的漏电流和更高的击穿电压。

公开(公告)号：US06479098B1

公开(公告)日：2002-11-12

申请号：US09747135

申请日：2000-12-26

申请人： Ming-Hwa Yoo ,  Yi-Lung Cheng ,  Szu-An Wu ,  Ying-Lang Wang

发明人： Ming-Hwa Yoo ,  Yi-Lung Cheng ,  Szu-An Wu ,  Ying-Lang Wang

IPC分类号： C23C1640

CPC分类号： H01J37/32477 ,  C23C16/4404 ,  Y10T428/2495 ,  Y10T428/265

摘要： A method for reducing contaminants in a processing chamber 10 having chamber plasma processing region components comprising the following steps. The chamber plasma processing region components are cleaned. The chamber is then seasoned as follows. A first USG layer is formed over the chamber plasma processing region components. An FSG layer is formed over the first USG layer. A second USG layer is formed over the FSG layer. Wherein the USG, FSG, and second USG layers comprise a UFU season film. A UFU season film coating the chamber plasma processing region components of a processing chamber comprises: an inner USG layer over the chamber plasma processing region components; an FSG layer over the inner USG layer; and an outer USG layer over the FSG layer.

摘要翻译： 一种用于减少具有室等离子体处理区域部件的处理室10中的污染物的方法，包括以下步骤。 腔室等离子体处理区域部件被清洁。 然后如下调节室。 在室等离子体处理区域部件上形成第一USG层。 在第一USG层上形成FSG层。 在FSG层上形成第二个USG层。 其中USG，FSG和第二USG层包括UFU季电影。 UFU季涂膜处理室的室等离子体处理区域部件包括：室上的内部USG层等离子体处理区域部件; 内部USG层上的FSG层; 以及FSG层上的外部USG层。

公开(公告)号：US06436791B1

公开(公告)日：2002-08-20

申请号：US09880259

申请日：2001-06-14

申请人： Shih-Chi Lin ,  Szu-An Wu ,  Ying-Lang Wang ,  Guey-Bao Huang

发明人： Shih-Chi Lin ,  Szu-An Wu ,  Ying-Lang Wang ,  Guey-Bao Huang

IPC分类号： H01L21302

CPC分类号： H01L21/76224

摘要： A method of forming a shallow trench isolation structure comprising the following steps. A substrate having an upper surface is provided. A pad oxide layer is formed upon the substrate. A nitride layer is formed over the pad oxide layer. The nitride layer having an upper surface. A trench is formed by etching the nitride layer, pad oxide layer and a portion of the substrate. The trench having a bottom and side walls. An oxide film is deposited upon the etched nitride layer surface, and the bottom and side walls of trench. The oxide film is removed from over the etched nitride layer surface, and the bottom of the trench to expose a portion of substrate within the trench. The removal of oxide film leaving oxide spacers over the trench side walls. Epitaxial silicon is selectively deposited over the exposed portion of substrate, filling the trench. A thermal oxide layer is formed over the epitaxial silicon, annealing the interface between the epitaxial silicon and the oxide spacers. The etched nitride layer and the oxide layer from over the etched substrate; and a portion of the oxide spacers extending above the surface of the etched substrate are removed, whereby the shallow trench isolation structure is formed within the trench.

摘要翻译： 一种形成浅沟槽隔离结构的方法，包括以下步骤。 提供具有上表面的基板。 衬底氧化层形成在衬底上。 在衬垫氧化物层上形成氮化物层。 氮化物层具有上表面。 通过蚀刻氮化物层，衬垫氧化物层和衬底的一部分来形成沟槽。 沟槽具有底部和侧壁。 在蚀刻的氮化物层表面和沟槽的底部和侧壁上沉积氧化物膜。 从蚀刻的氮化物层表面上方的氧化膜和沟槽的底部去除氧化膜，以露出沟槽内的衬底的一部分。 去除在沟槽侧壁上留下氧化物间隔物的氧化物膜。 外延硅被选择性地沉积在衬底的暴露部分上，填充沟槽。 在外延硅上形成热氧化层，退火外延硅与氧化物间隔物之间​​的界面。 蚀刻的氮化物层和来自蚀刻的衬底上的氧化物层; 并且去除在蚀刻的衬底的表面上方延伸的氧化物间隔物的一部分，由此在沟槽内形成浅沟槽隔离结构。

公开(公告)号：US06399522B1

公开(公告)日：2002-06-04

申请号：US09075115

申请日：1998-05-11

申请人： Chun-Ching Tsan ,  Hung-Ju Chien ,  Chun-Chang Chen ,  Ying-Lang Wang

发明人： Chun-Ching Tsan ,  Hung-Ju Chien ,  Chun-Chang Chen ,  Ying-Lang Wang

IPC分类号： H01L2131

CPC分类号： H01L21/02164 ,  C23C16/02 ,  C23C16/402 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02312 ,  H01L21/31612

摘要： A method of forming a PE-silane oxide layer with a greatly reduced particle count is described. A semiconductor substrate is provided over which a silicon oxide film is to be formed. The silicon oxide film is formed by the steps of: 1) pre-flowing a non-silane gas into a deposition chamber for at least two seconds whereby the pre-flowing step prevents formation of particles on the silicon oxide film, and 2) thereafter depositing a silicon oxide film by chemical vapor deposition by flowing a silane gas into the deposition chamber to complete formation of a silicon oxide film using plasma-enhanced chemical vapor deposition in the fabrication of an integrated circuit.

摘要翻译： 描述了形成具有大大降低的粒子数的PE-硅烷氧化物层的方法。 提供半导体衬底，在其上形成氧化硅膜。 氧化硅膜是通过以下步骤形成的：1）将非硅烷气体预先流入沉积室至少两秒钟，由此预流步骤防止在氧化硅膜上形成颗粒，2）之后 通过将硅烷气体流入沉积室中，通过化学气相沉积来沉积氧化硅膜，以在集成电路的制造中使用等离子体增强化学气相沉积来形成氧化硅膜。

公开(公告)号：US06395635B1

公开(公告)日：2002-05-28

申请号：US09206741

申请日：1998-12-07

申请人： Ying-Lang Wang ,  Jowei Dun

发明人： Ying-Lang Wang ,  Jowei Dun

IPC分类号： H01L21302

CPC分类号： H01L21/31053 ,  H01L21/3212

摘要： A CMP process is provided for the reduction of tungsten damascene residue and the elimination of surface scratch within the surface that is being polished. A three step polishing procedure of the ILD is followed by a two step buffing procedure of the ILD. The three step polishing procedure reduces the device defect count by eliminating damascene residue from the polished surface. The two step buffing procedure reduces micro scratch within the polished surface thus improving device throughput. A two step buffing procedure is applied to the IMD. Oxide buffing is applied and consists of a three step polishing procedure followed by a two step buffing procedure.

摘要翻译： 提供了一种CMP工艺，用于减少钨镶嵌残余物并消除正在抛光的表面内的表面划痕。 ILD的三步抛光程序之后是ILD的两步抛光程序。 三步抛光程序通过从抛光表面去除镶嵌残留物来减少设备缺陷计数。 两步抛光程序减少抛光表面内的微刮痕，从而提高设备的生产能力。 对IMD应用两步抛光程序。 应用氧化物抛光，并由三步抛光程序组成，其后是两步抛光程序。

公开(公告)号：US06323141B1

公开(公告)日：2001-11-27

申请号：US09541485

申请日：2000-04-03

申请人： Szu-Au Wu ,  Chun-Ching Tsan ,  Wen-Kung Cheng ,  Ying-Lang Wang

发明人： Szu-Au Wu ,  Chun-Ching Tsan ,  Wen-Kung Cheng ,  Ying-Lang Wang

IPC分类号： H01L2131

CPC分类号： H01L21/3145 ,  C23C16/24 ,  C23C16/402 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0276 ,  H01L21/28123 ,  H01L21/31612 ,  H01L21/32137 ,  H01L21/32139

摘要： A method for forming a patterned reflective layer first employs a substrate. There is then formed over the substrate a blanket reflective layer. There is then formed upon the blanket reflective layer an anti-reflective coating (ARC) layer formed employing a plasma enhanced chemical vapor deposition (PECVD) method employing a deposition gas composition comprising silane, nitrous oxide and argon. There is then formed upon the blanket anti-reflective coating (ARC) layer a blanket photoresist layer. There is then photoexposed and developed the blanket photoresist layer to form a patterned photoresist layer. There is then etched, while employing a first etch method, the blanket anti-reflective coating (ARC) layer to form a patterned anti-reflective coating (ARC) layer while employing the patterned photoresist layer as a first etch mask layer. Finally, there is then etched, while employing a second etch method, the blanket reflective layer to form the patterned reflective layer while employing at least the patterned anti-reflective coating (ARC) layer as a second etch mask layer.

摘要翻译： 用于形成图案化反射层的方法首先采用基板。 然后在衬底上形成覆盖层反射层。 然后在毯反射层上形成使用采用包含硅烷，一氧化二氮和氩的沉积气体组合物的等离子体增强化学气相沉积（PECVD）方法形成的抗反射涂层（ARC）层。 然后在橡皮布抗反射涂层（ARC）层上形成覆盖光致抗蚀剂层。 然后，将曝光的光刻胶照射并显影，以形成图案化的光致抗蚀剂层。 然后，在采用第一蚀刻方法的情况下，使用覆盖层抗反射涂层（ARC）层，同时使用图案化的光致抗蚀剂层作为第一蚀刻掩模层，来形成图案化的抗反射涂层（ARC）层。 最后，在采用第二蚀刻方法的同时，使用至少图案化的抗反射涂层（ARC）层作为第二蚀刻掩模层，同时使用第二蚀刻方法来蚀刻，以形成图案化的反射层。

公开(公告)号：US06232043B1

公开(公告)日：2001-05-15

申请号：US09318471

申请日：1999-05-25

申请人： Hway-Chi Lin ,  Yu-Ku Lin ,  Wen-Pin Chang ,  Ying-Lang Wang

发明人： Hway-Chi Lin ,  Yu-Ku Lin ,  Wen-Pin Chang ,  Ying-Lang Wang

IPC分类号： G03F700

CPC分类号： B24B37/013 ,  B24B37/042 ,  B24B49/12 ,  H01L21/31053 ,  H01L21/76224

摘要： A simple method for calculating the optimum amount of HDP deposited material that needs to be removed during CMP (without introducing dishing) is described. This method derives from our observation of a linear relationship between the amount of material that needs to be removed in order to achieve full planarization and a quantity called “OD for CMP density”. The latter is defined as PA×(100−PS) where PA is the percentage of active area relative to the total wafer area and PS is the percentage of sub-areas relative to the total wafer area. The sub-areas are regions in the dielectric, above the active areas, that are etched out prior to CMP. Thus, once the materials have been characterized, the optimum CMP removal thickness is readily calculated for a wide range of different circuit implementations.

摘要翻译： 描述了一种用于计算在CMP期间需要去除的HDP沉积材料的最佳量的简单方法（不引入凹陷）。 该方法来源于我们观察到需要去除的材料的量之间的线性关系以实现完全平坦化，并且称为“用于CMP密度的OD”。 后者被定义为PAx（100-PS），其中PA是相对于总晶片面积的有效面积的百分比，PS是相对于总晶片面积的子区域的百分比。 子区域是在CMP之前被蚀刻出的有源区域之上的电介质区域。 因此，一旦材料被表征，就可以很容易地计算各种不同电路实现的最佳CMP去除厚度。