公开(公告)号：US07460752B2

公开(公告)日：2008-12-02

申请号：US12154684

申请日：2008-05-24

Applicant: Morgan T. Johnson

Inventor： Morgan T. Johnson

IPC: G02B6/26 ,  G02B6/04 ,  G02B6/42 ,  G02B6/30

CPC classification number: G02B6/4222 ,  G01R31/2891 ,  G02B6/04 ,  G02B6/4226 ,  G02B6/4227

Abstract: A low-cost alignment system suitable for aligning a wafer to a test fixture includes a bundle of optical fibers wherein at least one fiber serves to deliver illumination to the alignment target from an end thereof, and a plurality of receiver fibers, each having ends with a known spatial relationship to the end of the illuminator fiber. The ends of the fiber bundle have a known spatial relationship to the fixture. In some embodiments, the fiber bundle is disposed within the fixture such that there is an unobscured optical path between the wafer and the receiving and illuminating ends of the fibers. In some embodiments, the fiber bundle is coupled to a light source and a light sensor mounted on the fixture. In some embodiments the alignment target is one or more bonding pads disposed on a wafer.

公开(公告)号：US07456643B2

公开(公告)日：2008-11-25

申请号：US11810237

申请日：2007-06-05

Applicant: Morgan T. Johnson

Inventor： Morgan T. Johnson

IPC: G01R31/02 ,  G01R31/26

CPC classification number: G01R1/07342 ,  G01R31/2886

Abstract: Access to integrated circuits of a wafer for concurrently performing two or more types of testing, is provided by bringing a wafer and an edge-extended wafer translator into an attached state. The edge-extended wafer translator having wafer-side contact terminals and inquiry-side contact terminals disposed thereon, a first set of wafer-side contact terminals being electrically coupled to a first set of inquiry-side contact terminals, and a second set of wafer-side contact terminals being electrically coupled to a second set of inquiry-side contact terminals. The edge-extended wafer translator having a central portion generally coextensive with the attached wafer, and an edge-extended portion extending beyond the boundary generally defined by the outer circumferential edge of the wafer. A first set of pads of at least one integrated circuit is electrically coupled to the first set of wafer-side contact terminals, and a second set of pads of the integrated circuit is electrically coupled to the second set of wafer-side contact terminals. The edge-extended wafer translator may be shaped such that its edge-extended portion is not coplanar with the central portion thereof.

Abstract translation: 通过使晶片和边缘延伸的晶片转换器进入附接状态来提供对晶片的集成电路的访问以同时执行两种或更多种类型的测试。 边缘延伸晶片转换器具有设置在其上的晶片侧接触端子和询问侧接触端子，第一组晶片侧接触端子电耦合到第一组查询侧接触端子，以及第二组晶片 侧接触端子电耦合到第二组询问侧接触端子。 边缘延伸晶片转换器具有与附接的晶片大致共同延伸的中心部分，以及延伸超出通常由晶片的外圆周边缘限定的边界的边缘延伸部分。 至少一个集成电路的第一组焊盘电耦合到第一组晶片侧接触端子，并且集成电路的第二组焊盘电耦合到第二组晶片侧接触端子。 边缘延伸晶片转换器可以被成形为使得其边缘延伸部分不与其中心部分共面。

公开(公告)号：US07455915B2

公开(公告)日：2008-11-25

申请号：US11349285

申请日：2006-02-06

Applicant: Morgan T. Johnson

Inventor： Morgan T. Johnson

IPC: B32B15/00 ,  H05K7/10

CPC classification number: H05K3/4015 ,  H05K3/027 ,  H05K3/341 ,  H05K2203/0191 ,  H05K2203/0769 ,  H05K2203/0786 ,  Y10T428/12493 ,  Y10T428/12507 ,  Y10T428/12514

Abstract: Application of a conductive material with a compliant underlayer onto selected pads of a substrate, includes forming at least one padstack, by patterning a sheet including a stack of material layers. Padstacks may include a first conductive top layer, one or more underlying layers, and a bottom attachment layer, such as a solder layer. At least one flexible, or compliant, layer is disposed in the sheet between the top and attachment layers. The compliant layer may be a conductive elastomer. The top layer of the padstacks are adhered to a soluble tape, and this composite structure is moved into place over the circuit board by means of a pick and place operation. The placement of the padstacks is followed by a solder reflow to adhere the padstacks to the contact pads of the substrate, and by a wash cycle with a solvent to remove the soluble tape.

Abstract translation: 将具有柔顺底层的导电材料施加到衬底的选定焊盘上，包括通过图案化包括一叠材料层的片材来形成至少一个衬垫堆叠。 垫片可以包括第一导电顶层，一个或多个下层和底部附着层，例如焊料层。 在顶部和附着层之间的片材中设置至少一个柔性或柔顺层。 柔性层可以是导电弹性体。 衬垫的顶层粘附到可溶性胶带上，并且通过拾取和放置操作将该复合结构移动到电路板上的适当位置。 焊盘的放置之后是焊料回流，以将焊盘粘附到衬底的接触焊盘，并且通过用溶剂洗涤循环以除去可溶性带。

公开(公告)号：US20080231302A1

公开(公告)日：2008-09-25

申请号：US12079202

申请日：2008-03-24

Applicant: Morgan T. Johnson

Inventor： Morgan T. Johnson

IPC: G01R31/04

CPC classification number: G01R1/0491

Abstract: A metallization pattern for a wafer translator provides a high density layout of interdigitated contact pads, suitable for component placement, along with larger contact pads suitable for connection to external equipment terminals. In another aspect, electrically conductive material may be added to, or removed from, the high density layout of interdigitated contact pads and larger contact pads to modify, or reconfigure, the electrical pathways of the wafer translator.

Abstract translation: 用于晶片转换器的金属化图案提供适合于元件放置的交错接触焊盘的高密度布局，以及适于连接到外部设备端子的较大接触焊盘。 在另一方面，可以将导电材料添加到交叉指接触垫和较大接触垫的高密度布局或从其移除，以修改或重新配置晶片转换器的电路径。

公开(公告)号：US07282931B2

公开(公告)日：2007-10-16

申请号：US10789305

申请日：2004-02-27

Applicant: Morgan T. Johnson

Inventor： Morgan T. Johnson

IPC: G01R1/073 ,  G01R31/28

CPC classification number: H01L24/72 ,  H01L21/76838 ,  H01L23/5382 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00

Abstract: A replacement for probe cards includes a full wafer contacter. A first surface of the full wafer contacter is brought into contact with, and the contacter is attached to, a wafer, thereby making electrical connection with at least a portion of the contact pads on each of a plurality of integrated circuits on the wafer. The full wafer contacter provides conductive pathways from the IC contact pads to a second surface of the full wafer contacter where a corresponding set of contact pads provide access to test systems and/or other devices. The contact pads on the second surface of the full wafer contacter are typically larger than the contact pads of the integrated circuits, and are typically spaced father apart from each other. The full wafer contacter is constructed to be suitable to provide access to the contact pads of the unsingulated integrated circuits during a wafer burn-in process.

Abstract translation: 探针卡的更换包括一个完整的晶圆连接器。 使全晶圆连接器的第一表面与晶片接触，并且连接器附接到晶片，从而与晶片上的多个集成电路中的每一个上的接触焊盘的至少一部分进行电连接。 全晶圆连接器提供从IC接触焊盘到全晶片连接器的第二表面的导电路径，其中相应的一组接触焊盘提供对测试系统和/或其它设备的访问。 全晶圆连接器的第二表面上的接触焊盘通常大于集成电路的接触焊盘，并且通常彼此间隔开。 全晶圆连接器被构造成适合于在晶片老化过程期间提供对未插拔集成电路的接触焊盘的访问。

公开(公告)号：US6043990A

公开(公告)日：2000-03-28

申请号：US871085

申请日：1997-06-09

Applicant: Morgan T. Johnson ,  David R. Ekstrom

Inventor： Morgan T. Johnson ,  David R. Ekstrom

IPC: H05K1/14 ,  H05K3/34 ,  H05K3/36 ,  B23K31/02 ,  B23K37/04 ,  H05K1/11

CPC classification number: H05K3/368 ,  H05K3/3436 ,  H05K1/144 ,  H05K2201/09145 ,  H05K2201/0949 ,  H05K2201/10234 ,  H05K2201/10992 ,  H05K2203/0165 ,  H05K2203/0278 ,  H05K2203/041 ,  H05K2203/167 ,  Y02P70/613

Abstract: A multiple circuit board package employing solder balls and method and apparatus for fabricating same is described. Two or more printed circuit boards and a plurality of electronic devices are joined together using solder balls. Alternatively, three or more printed circuit boards are joined together using the solder balls. A novel and improved solder ball connection is disclosed, along with a fixture for aligning and fixing the disposition of the pads and the solder balls during a heating cycle in which the circuit boards are placed under pressure while the solder balls are re-flowed for making an electrical connection.

Abstract translation: 描述了使用焊球的多重电路板封装及其制造方法和装置。 使用焊球将两个或多个印刷电路板和多个电子装置连接在一起。 或者，使用焊球将三个或更多个印刷电路板连接在一起。 公开了一种新颖且改进的焊球连接，以及用于在加热循环期间对准和固定焊盘和焊球的布置的固定装置，其中电路板被放置在压力下，同时焊球被重新流动以制造 电气连接。

公开(公告)号：US20140197858A1

公开(公告)日：2014-07-17

申请号：US13744180

申请日：2013-01-17

Applicant: Aaron Durbin ,  Morgan T. Johnson ,  Jose A. Santos

Inventor： Aaron Durbin ,  Morgan T. Johnson ,  Jose A. Santos

IPC: G01R31/26

CPC classification number: G01R31/2893 ,  G01R31/2831 ,  G01R31/2886

Abstract: A wafer translator and a wafer, removably attached to each other, provides the electrical connection to electrical contacts on integrated circuits on a wafer in such a manner that the electrical contacts are substantially undamaged in the process of making such electrical connections. Various embodiments of the present invention provide a gasketless sealing means for facilitating the formation by vacuum attachment of the wafer/wafer translator pair. In this way, no gasket is required to be disposed between the wafer and the wafer translator. Air, or gas, is evacuated from between the wafer and wafer translator through one or more evacuation pathways in the gasketless sealing means.

Abstract translation: 晶片转换器和可移除地彼此连接的晶片提供与晶片上的集成电路上的电触点的电连接，使得在制造这种电连接的过程中电触头基本上没有损坏。 本发明的各种实施例提供了一种无垫圈密封装置，用于通过真空附接晶片/晶片转换器对来促进形成。 以这种方式，不需要在晶片和晶片转换器之间设置衬垫。 空气或气体通过无垫圈密封装置中的一个或多个抽空通道从晶片和晶片转换器之间排出。

公开(公告)号：US08704544B2

公开(公告)日：2014-04-22

申请号：US13068152

申请日：2011-03-10

Applicant: Morgan T. Johnson

Inventor： Morgan T. Johnson

IPC: G01R31/20 ,  G01R31/28

CPC classification number: G01R31/2884 ,  G01R31/2851 ,  G01R31/2853 ,  G01R31/2855

Abstract: An apparatus, suitable for coupling a pads of integrated circuits on wafer to the pogo pins of a pogo tower in a test system without the need of a probe card, includes a body having a first surface and a second surface, the body having a substantially circular central portion, and a plurality of bendable arms extending outwardly from the central portion, each bendable arm having a connector tab disposed at the distal end thereof; a first plurality of contact terminals disposed on the second surface of the central portion of the body, the first plurality of contact terminals arranged in pattern to match the layout of pads on a wafer to be contacted; at least one contact terminal disposed on the first surface of the plurality of connector tabs; and a plurality of electrically conductive pathways disposed in the body such that each of the first plurality of contact terminals is electrically connected to a corresponding one of the contact terminals on the first surface of the connector tabs.

Abstract translation: 一种适于将晶片上的集成电路的焊盘与测试系统中的浮标塔的弹簧销耦合而不需要探针卡的装置包括具有第一表面和第二表面的本体，该主体具有基本上 圆形中心部分和从中心部分向外延伸的多个可弯曲臂，每个可弯曲臂具有设置在其远端处的连接片; 设置在所述主体的中心部分的第二表面上的第一多个接触端子，所述第一多个接触端子以图案布置以匹配待接触的晶片上的焊盘的布局; 至少一个接触端子，设置在所述多个连接器接头的第一表面上; 以及设置在所述主体中的多个导电通路，使得所述第一多个接触端子中的每一个电连接到所述连接器接头的第一表面上的对应的一个接触端子。

公开(公告)号：US08461024B2

公开(公告)日：2013-06-11

申请号：US13292037

申请日：2011-11-08

Applicant: Morgan T. Johnson

Inventor： Morgan T. Johnson

IPC: H01L21/00

CPC classification number: G01R31/2889 ,  G01R1/07307 ,  G01R31/2601 ,  H01L21/67 ,  H01L21/67253 ,  H01L21/6835 ,  H01L21/6838 ,  H01L21/76256 ,  H01L21/78 ,  H01L22/14 ,  H01L22/20 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2924/014

Abstract: A wafer translator is provided with a patterned layer of wafer bonding thermoset plastic and is removably attached with a wafer so as to form a wafer/wafer translator pair. The wafer translator acts as a mechanical support during a thinning process as well as during a wafer dicing operation. The singulated integrated circuits are then removed from the wafer translator. In some embodiments, wafer level testing of the integrated circuits on the wafer is performed subsequent to the wafer thinning process but before the wafer and wafer translator are separated. In other embodiments, wafer level testing of the integrated circuits on the wafer is performed subsequent to the wafer dicing operation but before the diced wafer and wafer translator are separated.

Abstract translation: 晶片转换器设置有晶片接合热固性塑料的图案化层，并且可移除地与晶片连接以形成晶片/晶片转换器对。 晶片转换器在薄化工艺期间以及在晶片切割操作期间用作机械支撑。 然后将单片化的集成电路从晶片转换器移除。 在一些实施例中，在晶片减薄处理之后但在晶片和晶片转换器分离之前执行晶片上的集成电路的晶片级测试。 在其他实施例中，在晶片切割操作之后，但是在切割的晶片和晶片转换器分离之前执行晶片上的集成电路的晶片级测试。

公开(公告)号：US20130021052A1

公开(公告)日：2013-01-24

申请号：US13068158

申请日：2011-03-10

Applicant: Morgan T. Johnson

Inventor： Morgan T. Johnson

IPC: G01R31/26

CPC classification number: G01R1/07371 ,  G01R1/04 ,  G01R1/0408 ,  G01R1/07314 ,  G01R1/07342 ,  G01R31/2887 ,  G01R31/2889

Abstract: Methods and apparatus for testing unsingulated integrated circuits on a wafer include adapting a wafer prober for use with full-wafer-contacter disposed on the wafer. Some embodiments include placing wafer on a chuck of the prober, aligning the wafer to a full-wafer contacter incorporated in the wafer prober, removably attaching the wafer to the full wafer contacter, separating the wafer from the chuck, and making electrical contact to one or more integrated circuits of the wafer by making physical contact with a surface of the full-wafer contacter that faces away from the wafer.

Abstract translation: 用于测试晶片上的非镶嵌集成电路的方法和装置包括使晶片探针适配用于设置在晶片上的全晶圆封装。 一些实施例包括将晶片放置在探测器的卡盘上，将晶片对准结晶在晶圆探针中的全晶圆封装，将晶片可移除地附接到全晶片连接器，将晶片与卡盘分离，并将电接触到一个 或更多的集成电路，通过与全晶圆连接器的远离​​晶片的表面进行物理接触。