公开(公告)号：US07948077B2

公开(公告)日：2011-05-24

申请号：US12134883

申请日：2008-06-06

申请人： Paul S. Andry ,  Evan G. Colgan ,  Lawrence S. Mok ,  Chirag S. Patel ,  David E. Seeger

发明人： Paul S. Andry ,  Evan G. Colgan ,  Lawrence S. Mok ,  Chirag S. Patel ,  David E. Seeger

IPC分类号： H01L23/473 ,  H01L23/52

CPC分类号： H01L23/473 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06589 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/15311 ,  H01L2224/0401

摘要： Apparatus and methods are provided for integrating microchannel cooling modules within high-density electronic modules (e.g., chip packages, system-on-a-package modules, etc.,) comprising multiple high-performance IC chips. Electronic modules are designed such that high-performance (high power) IC chips are disposed in close proximity to the integrated cooling module (or cooling plate) for effective heat extraction. Moreover, electronic modules which comprise large surface area silicon carriers with multiple chips face mounted thereon are designed such that integrated silicon cooling modules are rigidly bonded to the back surfaces of such chips to increase the structural integrity of the silicon carriers.

摘要翻译： 提供了用于将微通道冷却模块集成在包括多个高性能IC芯片的高密度电子模块（例如，芯片封装，系统级封装模块等）中的装置和方法。 电子模块被设计成使得高性能（大功率）IC芯片被布置成靠近集成冷却模块（或冷却板）以有效地提取热量。 此外，包括具有多个芯片面的大表面积硅载体的电子模块被设计成使得集成的硅冷却模块刚性地结合到这种芯片的背面以增加硅载体的结构完整性。

公开(公告)号：US20090301992A1

公开(公告)日：2009-12-10

申请号：US12542269

申请日：2009-08-17

申请人： Paul S. Andry ,  Chirag S. Patel

发明人： Paul S. Andry ,  Chirag S. Patel

IPC分类号： C23F1/00

CPC分类号： H01L23/50 ,  H01G4/236 ,  H01G4/33 ,  H01L21/486 ,  H01L23/49827 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

摘要： A chip carrier substrate includes a capacitor aperture and a laterally separated via aperture, each located within a substrate. The capacitor aperture is formed with a narrower linewidth and shallower depth than the via aperture incident to a microloading effect within a plasma etch method that is used for simultaneously etching the capacitor aperture and the via aperture within the substrate. Subsequently a capacitor is formed and located within the capacitor aperture and a via is formed and located within the via apertures. Various combinations of a first capacitor plate layer, a capacitor dielectric layer and a second capacitor plate layer may be contiguous with respect to the capacitor aperture and the via aperture.

摘要翻译： 芯片载体衬底包括电容器孔和横向分离的通孔，每个位于衬底内。 在用于同时蚀刻电容器孔径和衬底内的通孔孔径的等离子体蚀刻方法中，电容器孔径形成为比入射到微负载效应的通孔孔更窄的线宽和更浅的深度。 随后形成电容器并且位于电容器孔内并形成通孔并且位于通孔内。 第一电容器板层，电容器电介质层和第二电容器板层的各种组合可以相对于电容器孔径和通孔孔连续。

公开(公告)号：US20080173993A1

公开(公告)日：2008-07-24

申请号：US11624436

申请日：2007-01-18

申请人： Paul S. Andry ,  Chirag S. Patel

发明人： Paul S. Andry ,  Chirag S. Patel

IPC分类号： H01L23/02

CPC分类号： H01L23/50 ,  H01G4/236 ,  H01G4/33 ,  H01L21/486 ,  H01L23/49827 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

摘要： A chip carrier substrate includes a capacitor aperture and a laterally separated via aperture, each located within a substrate. The capacitor aperture is formed with a narrower linewidth and shallower depth than the via aperture incident to a microloading effect within a plasma etch method that is used for simultaneously etching the capacitor aperture and the via aperture within the substrate. Subsequently a capacitor is formed and located within the capacitor aperture and a via is formed and located within the via apertures. Various combinations of a first capacitor plate layer, a capacitor dielectric layer and a second capacitor plate layer may be contiguous with respect to the capacitor aperture and the via aperture.

摘要翻译： 芯片载体衬底包括电容器孔和横向分离的通孔，每个位于衬底内。 在用于同时蚀刻电容器孔径和衬底内的通孔孔径的等离子体蚀刻方法中，电容器孔径形成为比入射到微负载效应的通孔孔更窄的线宽和更浅的深度。 随后形成电容器并且位于电容器孔内并形成通孔并且位于通孔内。 第一电容器板层，电容器电介质层和第二电容器板层的各种组合可以相对于电容器孔径和通孔孔连续。

公开(公告)号：US07230334B2

公开(公告)日：2007-06-12

申请号：US10987985

申请日：2004-11-12

申请人： Paul S. Andry ,  Evan G. Colgan ,  Lawrence S. Mok ,  Chirag S. Patel ,  David E. Seeger

发明人： Paul S. Andry ,  Evan G. Colgan ,  Lawrence S. Mok ,  Chirag S. Patel ,  David E. Seeger

IPC分类号： H01L23/46

CPC分类号： H01L23/473 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06589 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/15311 ,  H01L2224/0401

摘要： Apparatus and methods are provided for integrating microchannel cooling modules within high-density electronic modules (e.g., chip packages, system-on-a-package modules, etc.,) comprising multiple high-performance IC chips. Electronic modules are designed such that high-performance (high power) IC chips are disposed in close proximity to the integrated cooling module (or cooling plate) for effective heat extraction. Moreover, electronic modules which comprise large surface area silicon carriers with multiple chips face mounted thereon are designed such that integrated silicon cooling modules are rigidly bonded to the back surfaces of such chips to increase the structural integrity of the silicon carriers.

摘要翻译： 提供了用于将微通道冷却模块集成在包括多个高性能IC芯片的高密度电子模块（例如，芯片封装，系统级封装模块等）中的装置和方法。 电子模块被设计成使得高性能（大功率）IC芯片被布置成靠近集成冷却模块（或冷却板）以有效地提取热量。 此外，包括具有多个芯片面的大表面积硅载体的电子模块被设计成使得集成的硅冷却模块刚性地结合到这种芯片的背面以增加硅载体的结构完整性。

公开(公告)号：US08115302B2

公开(公告)日：2012-02-14

申请号：US12134873

申请日：2008-06-06

申请人： Paul S. Andry ,  Evan G. Colgan

发明人： Paul S. Andry ,  Evan G. Colgan

IPC分类号： H01L23/473

CPC分类号： H01L23/473 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06589 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/15311 ,  H01L2224/0401

摘要： Apparatus and methods are provided for integrating microchannel cooling modules within high-density electronic modules (e.g., chip packages, system-on-a-package modules, etc.,) comprising multiple high-performance IC chips. Electronic modules are designed such that high-performance (high power) IC chips are disposed in close proximity to the integrated cooling module (or cooling plate) for effective heat extraction. Moreover, electronic modules which comprise large surface area silicon carriers with multiple chips face mounted thereon are designed such that integrated silicon cooling modules are rigidly bonded to the back surfaces of such chips to increase the structural integrity of the silicon carriers.

摘要翻译： 提供了用于将微通道冷却模块集成在包括多个高性能IC芯片的高密度电子模块（例如，芯片封装，系统级封装模块等）中的装置和方法。 电子模块被设计成使得高性能（大功率）IC芯片被布置成靠近集成冷却模块（或冷却板）以有效地提取热量。 此外，包括具有多个芯片面的大表面积硅载体的电子模块被设计成使得集成的硅冷却模块刚性地结合到这种芯片的背面以增加硅载体的结构完整性。

公开(公告)号：US07316831B2

公开(公告)日：2008-01-08

申请号：US10706842

申请日：2003-11-12

申请人： Paul S. Andry ,  Praveen Chaudhari ,  James P. Doyle ,  Eileen A. Galligan ,  James A. Lacey ,  Shui-Chih A. Lien ,  Minhua Lu

发明人： Paul S. Andry ,  Praveen Chaudhari ,  James P. Doyle ,  Eileen A. Galligan ,  James A. Lacey ,  Shui-Chih A. Lien ,  Minhua Lu

IPC分类号： G02F1/1337

CPC分类号： G02F1/133734 ,  G02F1/13378 ,  G02F2001/133765 ,  Y10T428/1009

摘要： A liquid crystal display device includes an alignment layer with constituent materials. The constituent materials have a stoichiometric relationship configured to provide a given pretilt angle. Liquid crystal material is provided in contact with the alignment layer. A method for forming an alignment layer for liquid crystal displays includes forming the alignment layer on a substrate by introducing an amount of material to adjust a stoichiometric ratio of constituent materials wherein the amount is determined to provide a given pretilt angle to the alignment layer. Ions are directed at the alignment layer to provide uniformity of the pretilt angle.

摘要翻译： 液晶显示装置包括具有构成材料的取向层。 构成材料具有配置成提供给定预倾角的化学计量关系。 液晶材料设置成与取向层接触。 用于形成液晶显示器取向层的方法包括：通过引入一定量的材料在基板上形成取向层，以调整其中所确定的量与取向层提供给定的预倾角的构成材料的化学计量比。 离子被引导到对准层以提供预倾角的均匀性。

公开(公告)号：US06566687B2

公开(公告)日：2003-05-20

申请号：US09765134

申请日：2001-01-18

申请人： Paul S. Andry ,  Frank R. Libsch ,  Takatoshi Tsujimura

发明人： Paul S. Andry ,  Frank R. Libsch ,  Takatoshi Tsujimura

IPC分类号： H01L2904

CPC分类号： H01L29/78633 ,  H01L21/0237 ,  H01L21/02532 ,  H01L21/02672 ,  H01L27/12 ,  H01L27/1277 ,  H01L29/66757

摘要： The present invention discloses a semiconductor device, a thin film transistor (TFT), and a process for forming a TFT. The semiconductor device according to the present invention comprises a top-gate type thin film transistor (TFT), said top-gate type TFT being formed on a substrate, said top-gate type TFT comprising: an insulating layer deposited on said substrate; a source electrode and a drain electrode formed from a metal-dopant compound, said metal-dopant compound being deposited on said insulating layer; a polycrystalline Si (poly-Si) layer deposited on said insulating layer and said source electrode and said drain electrode; an ohmic contact layer being formed between said metal-dopant compound and said poly-Si layer through migration of said dopant from said metal-dopant compound; a gate insulating layer deposited on said poly-Si layer; and a gate electrode formed on said gate insulating layer, wherein said poly-Si layer is crystallized by metal induced lateral crystallization.

摘要翻译： 本发明公开了半导体器件，薄膜晶体管（TFT）和TFT的形成工艺。 根据本发明的半导体器件包括顶栅型薄膜晶体管（TFT），所述顶栅型TFT形成在衬底上，所述顶栅型TFT包括：沉积在所述衬底上的绝缘层; 由金属 - 掺杂剂化合物形成的源电极和漏电极，所述金属 - 掺杂剂化合物沉积在所述绝缘层上; 沉积在所述绝缘层和所述源电极和所述漏电极上的多晶Si（多晶硅）层; 通过所述掺杂剂从所述金属掺杂剂化合物的迁移，在所述金属 - 掺杂剂化合物和所述多晶硅层之间形成欧姆接触层; 沉积在所述多晶硅层上的栅极绝缘层; 以及形成在所述栅极绝缘层上的栅电极，其中所述多晶硅层通过金属诱导的横向结晶而结晶。

公开(公告)号：US08855452B2

公开(公告)日：2014-10-07

申请号：US13353118

申请日：2012-01-18

申请人： Paul S. Andry ,  Russell A. Budd ,  Frank R. Libsch ,  Robert L. Wisnieff

发明人： Paul S. Andry ,  Russell A. Budd ,  Frank R. Libsch ,  Robert L. Wisnieff

IPC分类号： G02B6/34 ,  G02B6/12

CPC分类号： G02B6/4204 ,  G02B6/34

摘要： A silicon photonic chip is provided. An active silicon layer that includes a photonic device is on a front side of the silicon photonic chip. A silicon substrate that includes an etched backside cavity is on a backside of the silicon photonic chip. A microlens is integrated into the etched backside cavity. A buried oxide layer is located between the active silicon layer and the silicon substrate. The buried oxide layer is an etch stop for the etched backside cavity.

摘要翻译： 提供硅光子芯片。 包括光子器件的有源硅层位于硅光子芯片的前侧。 包括蚀刻的背面腔的硅衬底位于硅光子芯片的背面。 将微透镜集成到蚀刻的背面腔中。 掩埋氧化物层位于有源硅层和硅衬底之间。 掩埋氧化物层是用于蚀刻的背面腔的蚀刻停止。

公开(公告)号：US08559474B2

公开(公告)日：2013-10-15

申请号：US13604341

申请日：2012-09-05

申请人： Paul S. Andry ,  Russell A. Budd ,  Bing Dang ,  David Danovitch ,  Benjamin V. Fasano ,  Paul Fortier ,  Luc Guerin ,  Frank F. Libsch ,  Sylvain Ouimet ,  Chrirag S. Patel

发明人： Paul S. Andry ,  Russell A. Budd ,  Bing Dang ,  David Danovitch ,  Benjamin V. Fasano ,  Paul Fortier ,  Luc Guerin ,  Frank F. Libsch ,  Sylvain Ouimet ,  Chrirag S. Patel

IPC分类号： H01S5/024 ,  H01S5/18 ,  H01L23/28 ,  H01L23/18

CPC分类号： H01L27/1446 ,  G02B6/4204 ,  G02B6/4249 ,  G02B6/4257 ,  G02B6/428 ,  G02B6/4292 ,  H01L23/367 ,  H01L25/16 ,  H01L27/14625 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01S5/005 ,  H01S5/0224 ,  H01S5/02248 ,  H01S5/02276 ,  H01S5/02284 ,  H01S5/02407 ,  H01S5/02476 ,  H01S5/183 ,  H01S5/423 ,  H01L2924/014 ,  H01L2924/00

摘要： An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board.

摘要翻译： 公开了一种用于制造的光电（OE）封装或系统和方法，其包括具有布线的硅层。 硅层具有允许光通过的光通孔。 光耦合层结合到硅层，并且光耦合层包括多个微透镜，用于聚焦和/或准直光穿过光通孔。 多个OE元件耦合到硅层并与布线电连通。 至少一个OE元件被定位成与用于接收光的光通孔光学对准。 载体介于电互连元件之间。 载体位于硅层的布线和电路板之间，并且载体电连接到连接到硅层的布线的第一互连元件和连接到电路板的第二互连元件。

公开(公告)号：US08227264B2

公开(公告)日：2012-07-24

申请号：US13071894

申请日：2011-03-25

申请人： Paul S. Andry ,  Stephen L. Buchwalter ,  George A. Katopis ,  John U. Knickerbocker ,  Stelios G. Tsapepas ,  Bucknell C. Webb

发明人： Paul S. Andry ,  Stephen L. Buchwalter ,  George A. Katopis ,  John U. Knickerbocker ,  Stelios G. Tsapepas ,  Bucknell C. Webb

IPC分类号： H01L21/30

CPC分类号： H01L23/49827 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/00 ,  H01L2224/05552

摘要： An electronic device assembly is provided which includes a substrate, an interposer and an integrated circuit chip. The substrate is fabricated of a first material having a first thermal expansivity, and the interposer and integrated circuit chip are fabricated of a second material having a second thermal expansivity. The second thermal expansivity is different from the first thermal expansivity so that there is a coefficient of thermal expansion mismatch between the substrate and the interposer or chip. The interposer is coupled to the substrate via a first plurality of electrical contacts and an underfill adhesive at least partially surrounding the electrical contacts to bond the interposer to the substrate and thereby reduce strain on the first plurality of electrical contacts. The integrated circuit chip is coupled to the interposer via a second plurality of electrical contacts only, without use of an adhesive surrounding the second plurality of electrical contacts.

摘要翻译： 提供一种电子器件组件，其包括衬底，插入器和集成电路芯片。 衬底由具有第一热膨胀性的第一材料制成，并且插入器和集成电路芯片由具有第二热膨胀性的第二材料制成。 第二热膨胀性与第一热膨胀性不同，因此在衬底和插入件或芯片之间存在热膨胀失配系数。 插入器经由第一多个电触点和底部填充粘合剂耦合到基板，所述底部填充粘合剂至少部分地围绕电触点以将插入件结合到基板，从而减少第一多个电触点上的应变。 集成电路芯片仅通过第二多个电触点而耦合到插入器，而不使用围绕第二多个电触点的粘合剂。