公开(公告)号：US07183182B2

公开(公告)日：2007-02-27

申请号：US10669898

申请日：2003-09-24

申请人： Cyril Cabral, Jr. ,  Meikei Ieong ,  Jakub T. Kedzierski

发明人： Cyril Cabral, Jr. ,  Meikei Ieong ,  Jakub T. Kedzierski

IPC分类号： H01L21/425

CPC分类号： H01L29/66628 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/823835

摘要： A method of fabricating complementary metal oxide semiconductor (CMOS) field effect transistors which includes selective doping and full silicidation of a polysilicon material comprising the gate electrode of the transistor. In one embodiment, prior to silicidation, the polysilicon is amorphized. In a further embodiment, siliciding is performed at a low substrate temperature.

摘要翻译： 制造互补金属氧化物半导体（CMOS）场效应晶体管的方法，其包括选择性掺杂和包括晶体管的栅电极的多晶硅材料的全硅化。 在一个实施方案中，在硅化之前，多晶硅是非晶化的。 在另一个实施方案中，在低的衬底温度下进行硅化。

公开(公告)号：US07056782B2

公开(公告)日：2006-06-06

申请号：US10786901

申请日：2004-02-25

申请人： Ricky S. Amos ,  Diane C. Boyd ,  Cyril Cabral, Jr. ,  Richard D. Kaplan ,  Jakub T. Kedzierski ,  Victor Ku ,  Woo-Hyeong Lee ,  Ying Li ,  Anda C. Mocuta ,  Vijay Narayanan ,  An L. Steegen ,  Maheswaran Surendra

发明人： Ricky S. Amos ,  Diane C. Boyd ,  Cyril Cabral, Jr. ,  Richard D. Kaplan ,  Jakub T. Kedzierski ,  Victor Ku ,  Woo-Hyeong Lee ,  Ying Li ,  Anda C. Mocuta ,  Vijay Narayanan ,  An L. Steegen ,  Maheswaran Surendra

IPC分类号： H01L21/8238

CPC分类号： H01L21/76897 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/823835 ,  H01L29/66545 ,  H01L29/6656

摘要： The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.

公开(公告)号：US06982230B2

公开(公告)日：2006-01-03

申请号：US10291334

申请日：2002-11-08

申请人： Cyril Cabral, Jr. ,  Alessandro C. Callegari ,  Michael A. Gribelyuk ,  Paul C. Jamison ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Vijay Narayanan ,  Deborah A. Neumayer ,  Pushkar Ranade ,  Sufi Zafar

发明人： Cyril Cabral, Jr. ,  Alessandro C. Callegari ,  Michael A. Gribelyuk ,  Paul C. Jamison ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Vijay Narayanan ,  Deborah A. Neumayer ,  Pushkar Ranade ,  Sufi Zafar

IPC分类号： H01L21/31

CPC分类号： H01L21/02181 ,  C23C16/405 ,  C23C16/56 ,  H01L21/02189 ,  H01L21/02205 ,  H01L21/02271 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/31604 ,  H01L21/823857 ,  H01L27/0805 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating hafnium oxide and/or zirconium oxide films is provided. The methods include providing a mixture of Hf and/or Zr alkoxide dissolved, emulsified or suspended in a liquid; vaporizing at least the alkoxide and depositing the vaporized component at a temperature of greater than 400° C. The resultant film is dense, microcrystalline and is capable of self-passivation when treated in a hydrogen plasma or forming gas anneal.

公开(公告)号：US06979393B2

公开(公告)日：2005-12-27

申请号：US10055134

申请日：2002-01-22

申请人： Kenneth P. Rodbell ,  Panayotis C. Andricacos ,  Cyril Cabral, Jr. ,  Lynne M. Gignac ,  Cyprian E. Uzoh ,  Peter S. Locke

发明人： Kenneth P. Rodbell ,  Panayotis C. Andricacos ,  Cyril Cabral, Jr. ,  Lynne M. Gignac ,  Cyprian E. Uzoh ,  Peter S. Locke

IPC分类号： C25D3/38 ,  C25D5/00 ,  C25D5/10 ,  C25D7/12 ,  H05K3/42 ,  C25D5/02

CPC分类号： C25D5/10 ,  C25D3/38 ,  C25D5/00 ,  C25D7/123 ,  C25D21/02 ,  H05K3/423

摘要： A method for plating copper conductors on an electronic substrate and devices formed are disclosed. In the method, an electroplating copper bath that is filled with an electroplating solution kept at a temperature between about 0° C. and about 18° C. is first provided. A copper layer on the electronic substrate immersed in the electroplating solution is then plated either in a single step or in a dual-step deposition process. The dual-step deposition process is more suitable for depositing copper conductors in features that have large aspect ratios, such as a via hole in a dual damascene structure having an aspect ratio of diameter/depth of more than ⅓ or as high as 1/10. Various electroplating parameters are utilized to provide a short resistance transient in either the single step deposition or the dual-step deposition process. These parameters include the bath temperature, the bath agitation, the additive concentration in the plating bath, the plating current density utilized, the deposition rate of the copper film and the total thickness of the copper film deposited.

摘要翻译： 公开了一种在电子基板上镀铜导体的方法和形成的器件。 在该方法中，首先提供填充有保持在约0℃至约18℃之间的温度的电镀溶液的电镀铜浴。 然后将浸在电镀溶液中的电子基板上的铜层以单步骤或双步沉积工艺进行镀覆。 双步沉积方法更适合于在具有大纵横比的特征中沉积铜导体，例如具有大于1/3或高达1的直径/深度的纵横比的双镶嵌结构中的通孔 / 10。 各种电镀参数用于在单步沉积或双步沉积过程中提供短电阻瞬变。 这些参数包括浴温度，浴液搅拌，镀浴中的添加剂浓度，所用的电镀电流密度，铜膜的沉积速率和沉积的铜膜的总厚度。

公开(公告)号：US06921711B2

公开(公告)日：2005-07-26

申请号：US10605106

申请日：2003-09-09

申请人： Cyril Cabral, Jr. ,  Paul C. Jamison ,  Victor Ku ,  Ying Li ,  Vijay Narayanan ,  An L Steegen ,  Yun-Yu Wang ,  Kwong H. Wong

发明人： Cyril Cabral, Jr. ,  Paul C. Jamison ,  Victor Ku ,  Ying Li ,  Vijay Narayanan ,  An L Steegen ,  Yun-Yu Wang ,  Kwong H. Wong

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L21/443

CPC分类号： H01L29/66545 ,  H01L21/28079 ,  H01L29/4958

摘要： A structure and method for a metal replacement gate of a high performance device is provided. A sacrificial gate structure is first formed on an etch stop layer provided on a semiconductor substrate. A pair of spacers is provided on sidewalls of the sacrificial gate structure. The sacrificial gate structure is then removed, forming an opening. Subsequently, a metal gate including an first layer of metal such as tungsten, a diffusion barrier such as titanium nitride, and a second layer of metal such as tungsten is formed in the opening between the spacers.

摘要翻译： 提供了一种用于高性能器件的金属替换栅极的结构和方法。 首先在设置在半导体衬底上的蚀刻停止层上形成牺牲栅极结构。 在牺牲栅极结构的侧壁上设置一对间隔物。 然后去除牺牲栅极结构，形成开口。 随后，在间隔件之间的开口中形成包括诸如钨的第一金属层的金属栅，诸如氮化钛的扩散阻挡层和诸如钨的第二金属层。

公开(公告)号：US06909145B2

公开(公告)日：2005-06-21

申请号：US10252661

申请日：2002-09-23

申请人： Cyril Cabral, Jr. ,  Lawrence A. Clevenger ,  Louis L. Hsu ,  Joseph F. Shepard, Jr. ,  Kwong Hon Wong

发明人： Cyril Cabral, Jr. ,  Lawrence A. Clevenger ,  Louis L. Hsu ,  Joseph F. Shepard, Jr. ,  Kwong Hon Wong

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/6653 ,  H01L21/28061 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/6659

摘要： A method and structure for a metal oxide semiconductor transistor having a substrate, a well region in the substrate, source and drain regions on opposite sides of the well region in the substrate, a gate insulator over the well region of the substrate, a polysilicon gate conductor over the gate insulator, and metallic spacers on sides of the gate conductor.

摘要翻译： 一种金属氧化物半导体晶体管的方法和结构，其具有衬底，衬底中的阱区，衬底中的阱区的相对侧上的源极和漏极区，衬底的阱区上的栅极绝缘体，多晶硅栅极 栅极绝缘体上的导体，以及栅极导体侧面的金属间隔物。

公开(公告)号：US06846734B2

公开(公告)日：2005-01-25

申请号：US10300165

申请日：2002-11-20

申请人： Ricky Amos ,  Katayun Barmak ,  Diane C. Boyd ,  Cyril Cabral, Jr. ,  Meikei Leong ,  Thomas S. Kanarsky ,  Jakub Tadeusz Kedzierski

发明人： Ricky Amos ,  Katayun Barmak ,  Diane C. Boyd ,  Cyril Cabral, Jr. ,  Meikei Leong ,  Thomas S. Kanarsky ,  Jakub Tadeusz Kedzierski

IPC分类号： H01L27/092 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/3205 ,  H01L21/44 ,  H01L21/4763

CPC分类号： H01L21/823835 ,  H01L21/28097 ,  H01L21/823842 ,  H01L21/84 ,  H01L29/66545

摘要： Methods of forming complementary metal oxide semiconductor (CMOS) devices having multiple-threshold voltages which are easily tunable are provided. Total salicidation with a metal bilayer (representative of the first method of the present invention) or metal alloy (representative of the second method of the present invention) is provided. CMOS devices having multiple-threshold voltages provided by the present methods are also described.

摘要翻译： 提供了形成具有易于调节的多阈值电压的互补金属氧化物半导体（CMOS）器件的方法。 提供了用金属双层（代表本发明的第一种方法）或金属合金（代表本发明的第二种方法）的总的水杨酸化。 还描述了通过本方法提供的具有多阈值电压的CMOS器件。

公开(公告)号：US06794226B2

公开(公告)日：2004-09-21

申请号：US10374395

申请日：2003-02-26

申请人： Cyril Cabral, Jr. ,  Lawrence Clevenger ,  Louis Lu-Chen Hsu ,  Keith Kwong Hon Wong

发明人： Cyril Cabral, Jr. ,  Lawrence Clevenger ,  Louis Lu-Chen Hsu ,  Keith Kwong Hon Wong

IPC分类号： H01L2182

CPC分类号： H01L21/76849 ,  H01L21/7687 ,  H01L21/76888 ,  H01L23/5258 ,  H01L27/0629 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure that includes at least one circuit element of a fuse, a diffusion barrier or a capacitor that is formed by refractory metal-silicon-nitrogen is disclosed. A method for fabricating such semiconductor structure that includes a fuse element, a diffusion barrier, a resistor or a capacitor by a refractory metal-silicon-nitrogen material is further disclosed. A suitable refractory metal-silicon-nitrogen material to be used is TaSiN which provides a wide range of resistivity by changing the ratio of Ta:Si:N. The invention provides the benefit that the various components of diffusion barriers, fuses, capacitors and resistors may be formed by a single deposition process of a TaSiN layer, the various components are then selectively masked and treated by either heat-treating or ion-implantation to vary their resistivity selectively while keeping the other shielded elements at the same resistivity.

摘要翻译： 公开了一种半导体结构，其包括由难熔金属 - 硅 - 氮形成的熔丝，扩散阻挡层或电容器的至少一个电路元件。 还公开了一种通过难熔金属硅 - 氮材料制造这种半导体结构的方法，其包括熔丝元件，扩散阻挡层，电阻器或电容器。 要使用的合适的难熔金属 - 硅 - 氮材料是TaSiN，其通过改变Ta:Si:N的比例来提供宽范围的电阻率。 本发明提供了通过TaSiN层的单个沉积工艺可以形成扩散阻挡层，保险丝，电容器和电阻器的各种组件的优点，然后通过热处理或离子注入对各种组分进行选择性掩蔽和处理， 选择性地改变其电阻率，同时保持其他屏蔽元件具有相同的电阻率。

公开(公告)号：US06524908B2

公开(公告)日：2003-02-25

申请号：US09872603

申请日：2001-06-01

申请人： Cyril Cabral, Jr. ,  Lawrence Clevenger ,  Louis Hsu ,  Keith Kwong Hon Wong

发明人： Cyril Cabral, Jr. ,  Lawrence Clevenger ,  Louis Hsu ,  Keith Kwong Hon Wong

IPC分类号： H01L218242

CPC分类号： H01L28/75 ,  C23C14/0073 ,  C23C14/0641 ,  H01L21/2855 ,  H01L21/28568

摘要： A method forforming a refractory metal-silicon-nitrogen capacitor in a semiconductor structure and the structure formed are described. In the method, a pre-processed semiconductor substrate is first positioned in a sputtering chamber. Ar gas is then flown into the sputtering chamber to sputter deposit a first refractory metal-silicon-nitrogen layer on the substrate from a refractory metal silicide target, or from two targets of a refractory metal and a silicon. N2 gas is then flown into the sputtering chamber until that the concentration of N2 gas in the chamber is at least 35% to sputter deposit a second refractory metal-silicon-nitrogen layer on top of the first refractory metal-silicon-nitrogen layer. The N2 gas flow is then stopped to sputter deposit a third refractory metal-silicon-nitrogen layer on top of the second refractory metal-silicon-nitrogen layer. The multi-layer stack of the refractory metal-silicon-nitrogen is then photolithographically formed into a capacitor.

摘要翻译： 描述了一种在半导体结构中形成难熔金属 - 硅 - 氮电容器的方法和形成的结构。 在该方法中，首先将预处理的半导体衬底定位在溅射室中。 然后将Ar气体流入溅射室，以从耐火金属硅化物靶或从难熔金属和硅的两个靶溅射沉积在衬底上的第一难熔金属 - 硅 - 氮层。 然后将N 2气体流入溅射室，直到室内的N 2气体的浓度至少为35％，以在第一难熔金属 - 硅 - 氮层的顶部溅射沉积第二难熔金属 - 硅 - 氮层。 然后停止N 2气流以在第二难熔金属 - 硅 - 氮层的顶部溅射沉积第三难熔金属 - 硅 - 氮层。 然后将难熔金属硅 - 氮的多层堆叠光刻形成电容器。

公开(公告)号：US06503833B1

公开(公告)日：2003-01-07

申请号：US09712264

申请日：2000-11-15

申请人： Atul Champaklal Ajmera ,  Cyril Cabral, Jr. ,  Roy Arthur Carruthers ,  Kevin Kok Chan ,  Guy Moshe Cohen ,  Paul Michael Kozlowski ,  Christian Lavoie ,  Joseph Scott Newbury ,  Ronnen Andrew Roy

发明人： Atul Champaklal Ajmera ,  Cyril Cabral, Jr. ,  Roy Arthur Carruthers ,  Kevin Kok Chan ,  Guy Moshe Cohen ,  Paul Michael Kozlowski ,  Christian Lavoie ,  Joseph Scott Newbury ,  Ronnen Andrew Roy

IPC分类号： H01L2144

CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L29/1054 ,  H01L29/7834

摘要： A method of forming a semiconductor substrate (and resultant structure), includes providing a semiconductor substrate to be silicided including a source and drain formed therein on respective sides of a gate, depositing a metal film over the gate, source and drain regions, reacting the metal film with Si at a first predetermined temperature, to form a metal-silicon alloy, etching the unreacted metal, depositing a silicon film over the source drain and gate regions, annealing the substrate at a second predetermined temperature, to form a metal-Si2 alloy, and selectively etching the unreacted Si.

摘要翻译： 一种形成半导体衬底（及其结构）的方法，包括在栅极的各个侧面上设置硅化物半导体衬底，该半导体衬底包括形成在其中的源极和漏极，在栅极，源极和漏极区域上沉积金属膜， 在第一预定温度下具有Si的金属膜，以形成金属 - 硅合金，蚀刻未反应的金属，在源极漏极和栅极区域上沉积硅膜，在第二预定温度下退火衬底以形成金属-Si2 合金，并选择性地蚀刻未反应的Si。