公开(公告)号：US10141452B2

公开(公告)日：2018-11-27

申请号：US15864033

申请日：2018-01-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Daigo Ito ,  Daisuke Matsubayashi ,  Masaharu Nagai ,  Yoshiaki Yamamoto ,  Takashi Hamada ,  Yutaka Okazaki ,  Shinya Sasagawa ,  Motomu Kurata ,  Naoto Yamade

IPC: H01L29/786 ,  H01L21/46 ,  H01L27/12 ,  H01L29/66 ,  H01L21/425 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/24 ,  H01L29/778

Abstract: A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, a second metal oxide layer over the oxide semiconductor layer, a gate insulating layer over the second metal oxide layer, a second insulating layer over the second metal oxide layer, and a gate electrode layer over the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer. The second insulating layer includes a region in contact with the gate insulating layer. The oxide semiconductor layer includes first to third regions. The first region includes a region overlapping with the gate electrode layer. The second region, which is between the first and third regions, includes a region overlapping with the gate insulating layer or the second insulating layer. The second and third regions each include a region containing an element N (N is phosphorus, argon, or xenon).

公开(公告)号：US09922994B2

公开(公告)日：2018-03-20

申请号：US15332006

申请日：2016-10-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Ryota Hodo ,  Motomu Kurata ,  Shinya Sasagawa ,  Satoru Okamoto ,  Shunpei Yamazaki

IPC: H01L27/12 ,  H01L29/66 ,  H01L21/02 ,  H01L21/467 ,  H01L21/463 ,  H01L21/768 ,  H01L29/786 ,  H01L23/535 ,  H01L23/522 ,  H01L29/778 ,  H01L23/532

CPC classification number: H01L27/1225 ,  H01L21/02565 ,  H01L21/463 ,  H01L21/467 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L27/1288 ,  H01L29/66969 ,  H01L29/7781 ,  H01L29/7782 ,  H01L29/78603 ,  H01L29/7869

Abstract: First to third insulators are successively formed in this order over a first conductor over a semiconductor substrate; a hard mask with a first opening is formed thereover; a resist mask with a second opening is formed thereover; a third opening is formed in the third insulator; a fourth opening is formed in the second insulator; the resist mask is removed; a fifth opening is formed in the first to third insulators; a second conductor is formed to cover an inner wall and a bottom surface of the fifth opening; a third conductor is formed thereover; polishing treatment is performed so that the hard mask is removed, and that levels of top surfaces of the second and third conductors and the third insulator are substantially equal to each other; and an oxide semiconductor is formed thereover. The second insulator is less permeable to hydrogen than the first and third insulators, the second conductor is less permeable to hydrogen than the third conductor.

公开(公告)号：US09875910B2

公开(公告)日：2018-01-23

申请号：US15226003

申请日：2016-08-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Motomu Kurata ,  Shinya Sasagawa ,  Fumika Taguchi ,  Yoshinori Ieda

IPC: H01L21/3105 ,  H01L21/3213 ,  H01L27/12 ,  H01L21/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535

CPC classification number: H01L27/1288 ,  H01L21/31053 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/486 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/535 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/124

Abstract: It is an object to reduce defective conduction in a wiring board or a semiconductor device whose integration degree is increased. It is another object to manufacture a highly reliable wiring board or semiconductor device with high yield. In a wiring board or a semiconductor device having a multilayer wiring structure, a conductive layer having a curved surface is used in connection between conductive layers used for the wirings. The top of a conductive layer in a lower layer exposed by removal of an insulating layer therearound has a curved surface, so that coverage of the conductive layer in the lower layer with a conductive layer in an upper layer stacked thereover can be favorable. A conductive layer is etched using a resist mask having a curved surface, so that a conductive layer having a curved surface is formed.

公开(公告)号：US09842940B2

公开(公告)日：2017-12-12

申请号：US15062268

申请日：2016-03-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya Sasagawa ,  Motomu Kurata ,  Kazuya Hanaoka ,  Yoshiyuki Kobayashi ,  Daisuke Matsubayashi

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/04 ,  H01L29/24

CPC classification number: H01L29/78696 ,  H01L29/045 ,  H01L29/24 ,  H01L29/7869

Abstract: A semiconductor device with favorable electrical characteristics is provided. The semiconductor device includes an insulating layer, a semiconductor layer over the insulating layer, a source electrode layer and a drain electrode layer electrically connected to the semiconductor layer, a gate insulating film over the semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode layer overlapping with part of the semiconductor layer, part of the source electrode layer, and part of the drain electrode layer with the gate insulating film therebetween. A cross section of the semiconductor layer in the channel width direction is substantially triangular or substantially trapezoidal. The effective channel width is shorter than that for a rectangular cross section.

公开(公告)号：US09773915B2

公开(公告)日：2017-09-26

申请号：US14293115

申请日：2014-06-02

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shinya Sasagawa ,  Motomu Kurata ,  Kazuya Hanaoka ,  Suguru Hondo

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78609

Abstract: A semiconductor device using oxide semiconductor with favorable electrical characteristics, or a highly reliable semiconductor device is provided. A semiconductor device is manufactured by: forming an oxide semiconductor layer over an insulating surface; forming source and drain electrodes over the oxide semiconductor layer; forming an insulating film and a conductive film in this order over the oxide semiconductor layer and the source and drain electrodes; etching part of the conductive film and insulating film to form a gate electrode and a gate insulating layer, and etching part of the upper portions of the source and drain electrodes to form a first covering layer containing a constituent element of the source and drain electrodes and in contact with the side surface of the gate insulating layer; oxidizing the first covering layer to form a second covering layer; and forming a protective insulating layer containing an oxide over the second covering layer.

公开(公告)号：US09728648B2

公开(公告)日：2017-08-08

申请号：US14992570

申请日：2016-01-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya Sasagawa ,  Motomu Kurata

IPC: H01L29/786 ,  H01L27/1156 ,  H01L29/66

CPC classification number: H01L29/78606 ,  H01L27/1156 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

Abstract: A miniaturized transistor having excellent electrical characteristics is provided with high yield. Further, a semiconductor device including the transistor and having high performance and high reliability is manufactured with high productivity. In a semiconductor device including a transistor in which an oxide semiconductor film including a channel formation region and low-resistance regions between which the channel formation region is sandwiched, a gate insulating film, and a gate electrode layer whose top surface and side surface are covered with an insulating film including an aluminum oxide film are stacked, a source electrode layer and a drain electrode layer are in contact with part of the oxide semiconductor film and the top surface and a side surface of the insulating film including an aluminum oxide film.

公开(公告)号：US09691904B2

公开(公告)日：2017-06-27

申请号：US15221656

申请日：2016-07-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya Sasagawa ,  Motomu Kurata

IPC: H01L29/786 ,  H01L29/76 ,  H01L29/26 ,  H01L29/24 ,  H01L29/423

CPC classification number: H01L29/7869 ,  H01L29/24 ,  H01L29/247 ,  H01L29/263 ,  H01L29/42356 ,  H01L29/42364 ,  H01L29/78693 ,  H01L29/78696

Abstract: To give favorable electrical characteristics to a semiconductor device. The semiconductor device includes an insulating layer, a semiconductor layer over the insulating layer, a pair of electrodes over the semiconductor layer and each electrically connected to the semiconductor layer, a gate electrode over the semiconductor layer, and a gate insulating layer between the semiconductor layer and the gate electrode. The insulating layer includes an island-shaped projecting portion. A top surface of the projecting portion of the insulating layer is in contact with a bottom surface of the semiconductor layer, and is positioned on an inner side of the semiconductor layer when seen from above. The pair of electrodes covers part of a top surface and part of side surfaces of the semiconductor layer. Furthermore, the gate electrode and the gate insulating layer cover side surfaces of the projecting portion of the insulating layer.

公开(公告)号：US09647129B2

公开(公告)日：2017-05-09

申请号：US14755670

申请日：2015-06-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Motomu Kurata ,  Ryota Hodo ,  Shinya Sasagawa ,  Yuki Hata

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/24 ,  H01L23/485 ,  H01L27/1156 ,  H01L27/06 ,  H01L21/8258 ,  H01L27/092

CPC classification number: H01L27/1207 ,  H01L21/8258 ,  H01L23/485 ,  H01L23/535 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1156 ,  H01L27/124 ,  H01L29/24 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: To provide a semiconductor device which occupies a small area and is highly integrated. The semiconductor device includes an oxide semiconductor layer, an electrode layer, and a contact plug. The electrode layer includes one end portion in contact with the oxide semiconductor layer and the other end portion facing the one end portion. The other end portion includes a semicircle notch portion when seen from the above. The contact plug is in contact with the semicircle notch portion.

公开(公告)号：US09601632B2

公开(公告)日：2017-03-21

申请号：US14021618

申请日：2013-09-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hideomi Suzawa ,  Shinya Sasagawa ,  Motomu Kurata ,  Masashi Tsubuku

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/66969 ,  H01L21/02565 ,  H01L27/1225 ,  H01L27/127 ,  H01L27/14616 ,  H01L27/14689 ,  H01L29/7869 ,  H01L29/78696

Abstract: The on-state characteristics of a transistor are improved and thus, a semiconductor device capable of high-speed response and high-speed operation is provided. A highly reliable semiconductor device showing stable electric characteristics is made. The semiconductor device includes a transistor including a first oxide layer; an oxide semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a second oxide layer over the oxide semiconductor layer; a gate insulating layer over the second oxide layer; and a gate electrode layer over the gate insulating layer. An end portion of the second oxide layer and an end portion of the gate insulating layer overlap with the source electrode layer and the drain electrode layer.

公开(公告)号：US09520410B2

公开(公告)日：2016-12-13

申请号：US14446934

申请日：2014-07-30

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Satoshi Murakami ,  Motomu Kurata ,  Hiroyuki Hata ,  Mitsuhiro Ichijo ,  Takashi Ohtsuki ,  Aya Anzai ,  Masayuki Sakakura

IPC: H01L27/14 ,  H01L29/04 ,  H01L29/15 ,  H01L31/036 ,  H01L27/12 ,  H01L27/32 ,  H01L51/52 ,  H01L33/60 ,  H01L51/00 ,  H01L51/56

CPC classification number: H04N5/655 ,  G06F3/02 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/3244 ,  H01L27/3258 ,  H01L27/3276 ,  H01L33/60 ,  H01L51/0005 ,  H01L51/5246 ,  H01L51/56 ,  H01L2224/4847 ,  H01L2227/323 ,  H01L2251/5323 ,  H04N5/642

Abstract: The present invention provides a method for manufacturing a highly reliable display device at a low cost with high yield. According to the present invention, a step due to an opening in a contact is covered with an insulating layer to reduce the step, and is processed into a gentle shape. A wiring or the like is formed to be in contact with the insulating layer and thus the coverage of the wiring or the like is enhanced. In addition, deterioration of a light-emitting element due to contaminants such as water can be prevented by sealing a layer including an organic material that has water permeability in a display device with a sealing material. Since the sealing material is formed in a portion of a driver circuit region in the display device, the frame margin of the display device can be narrowed.