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84 条记录 (耗时 0.026 秒)

    Voltage detecting circuit
    44.
    发明授权
    Voltage detecting circuit 失效
    电压检测电路

    公开(公告)号：US4922133A

    公开(公告)日：1990-05-01

    申请号：US226097

    申请日：1988-07-29

    申请人： Hiroshi Iwahashi ,  Hiroto Nakai ,  Masamichi Asano

    发明人： Hiroshi Iwahashi ,  Hiroto Nakai ,  Masamichi Asano

    IPC分类号： H01L21/8247 ,  G11C16/06 ,  G11C17/00 ,  H01L21/822 ,  H01L27/04 ,  H01L29/788 ,  H01L29/792 ,  H03K5/08 ,  H03K17/30

    CPC分类号： H03K17/302 ,  H03K5/08

    摘要： A voltage detecting circuit comprising a voltage-input terminal for receiving a first voltage or a second voltage higher than the first voltage, switch means connected between the voltage-input terminal and a first node, and an inverter circuit having an input terminal coupled to the first node and an output terminal coupled to a second node. The switch circuit is turned on when the voltage at the voltage-input terminal is higher than a predetermined value which is between the higher than the first voltage and lower than the second voltage, and is turned off when the voltage at the voltage-input terminal is lower than the predetermined value. The inverter circuit includes a first transistor having a source-drain path coupled between a first power-source potential terminal and the second node, a current control section for maintaining a current flowing through the source-drain path of the first transistor at a predetermined value, and a second transistor having a source-drain path connected between the second node and a second power-source potential terminal and a gate coupled to the first node.

    摘要翻译： 一种电压检测电路，包括用于接收高于第一电压的第一电压或第二电压的电压输入端子，连接在电压输入端子和第一节点之间的开关装置，以及具有耦合到第一电压的输入端子的反相器电路 第一节点和耦合到第二节点的输出终端。 当电压输入端子的电压高于高于第一电压且低于第二电压的预定值时，开关电路导通，并且当电压输入端子处的电压 低于预定值。 逆变器电路包括：第一晶体管，其具有耦合在第一电源电位端子和第二节点之间的源极 - 漏极路径;电流控制部分，用于将流过第一晶体管的源极 - 漏极通路的电流保持在预定值 以及第二晶体管，其源极 - 漏极路径连接在第二节点和第二电源电位端子之间，栅极耦合到第一节点。

    Electrostatic discharge protection circuit with variable limiting threshold for MOS device
    45.
    发明授权
    Electrostatic discharge protection circuit with variable limiting threshold for MOS device 失效
    MOS器件具有可变限流阈值的静电放电保护电路

    公开(公告)号：US4692834A

    公开(公告)日：1987-09-08

    申请号：US761707

    申请日：1985-08-02

    申请人： Hiroshi Iwahashi ,  Masamichi Asano ,  Akira Narita

    发明人： Hiroshi Iwahashi ,  Masamichi Asano ,  Akira Narita

    IPC分类号： H01L27/06 ,  H02H9/04 ,  H02H3/20

    CPC分类号： H02H9/046

    摘要： An electrostatic discharge protection circuit is provided with a variable threshold for limiting the potential of an input signal having a given high or low voltage, and is adapted to an EPROM containing an input MOS transistor which is responsive to the input signal. The protection circuit is associated with an input terminal for receiving the input signal. The input terminal is coupled to the gate of the input MOS transistor. The protection circuit also includes a circuit element for limiting or suppressing the input signal potential at the variable threshold. The gate of the input MOS transistor receives the potential limited signal from the circuit element. The circuit element is responsive to a given threshold control potential. The variable threshold is enhanced by the given threshold control potential when a high-voltage input signal is applied to the input terminal.

    摘要翻译： 静电放电保护电路具有用于限制具有给定高或低电压的输入信号的电位的可变阈值，并且适用于包含响应于输入信号的输入MOS晶体管的EPROM。 保护电路与用于接收输入信号的输入端相关联。 输入端耦合到输入MOS晶体管的栅极。 保护电路还包括用于限制或抑制在可变阈值处的输入信号电位的电路元件。 输入MOS晶体管的栅极接收来自电路元件的电位限制信号。 电路元件响应给定的阈值控制电位。 当将高电压输入信号施加到输入端时，通过给定的阈值控制电位增强可变阈值。

    Semiconductor memory with delay means to reduce peak currents
    46.
    发明授权
    Semiconductor memory with delay means to reduce peak currents 失效
    具有延迟的半导体存储器，以减少峰值电流

    公开(公告)号：US4556961A

    公开(公告)日：1985-12-03

    申请号：US379852

    申请日：1982-05-19

    申请人： Hiroshi Iwahashi ,  Masamichi Asano

    发明人： Hiroshi Iwahashi ,  Masamichi Asano

    IPC分类号： G11C5/06 ,  G11C8/14 ,  G11C11/40 ,  G11C7/00

    CPC分类号： G11C5/063 ,  G11C8/14

    摘要： A semiconductor device comprises a plurality of data supply circuits, output circuits for producing a plurality of data delivered from the data supply circuit and delay circuit for transferring respective data from each data supply circuit to a different output circuit with a different delay time. Each data supply circuit includes a plurality of row lines, a row decoder for selecting the row line in response to an address signal, a plurality of memory cell arrays including memory cells selectively driven by the row line and storing data, a plurality of column lines to receive data read out from the memory cell array, and a column decoder for selecting said column lines. The delay circuit prevents a plurality of data from being simultaneously outputted.

    摘要翻译： 半导体器件包括多个数据提供电路，用于产生从数据提供电路传送的多个数据的输出电路和用于将各个数据从每个数据提供电路传送到具有不同延迟时间的不同输出电路的延迟电路。 每个数据提供电路包括多行行，行解码器，用于响应于地址信号选择行行;多个存储单元阵列，包括由行行有选择地驱动并存储数据的存储单元;多个列线 以接收从存储单元阵列读出的数据，以及列解码器，用于选择所述列线。 延迟电路防止多个数据被同时输出。

    Semiconductor integrated circuit
    47.
    发明授权
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号：US4542485A

    公开(公告)日：1985-09-17

    申请号：US337969

    申请日：1982-01-08

    申请人： Hiroshi Iwahashi ,  Masamichi Asano

    发明人： Hiroshi Iwahashi ,  Masamichi Asano

    IPC分类号： G05F3/24 ,  G11C5/00 ,  G11C5/14 ,  G11C7/22 ,  G11C8/00 ,  G11C8/06 ,  G11C8/10 ,  G11C17/08 ,  G11C13/00 ,  G11C11/40

    CPC分类号： G11C5/147 ,  G05F3/242 ,  G11C17/08 ,  G11C5/00 ,  G11C7/22 ,  G11C8/00 ,  G11C8/06 ,  G11C8/10

    摘要： A semiconductor integrated circuit comprises a first MOS transistor connected at the drain to a power source terminal of a high potential power source and supplied at the gate with a predetermined voltage, a logic circuit including MOS transistors provided between the power source terminal and a circuit point at a potential and operating in a potential range between the high potential and the circuit point, and a circuit for making the potential at the circuit point coincide with the potential at the source of the first MOS transistor.

    摘要翻译： 半导体集成电路包括：第一MOS晶体管，其在漏极处连接到高电位电源的电源端子，并在栅极处提供预定电压;逻辑电路，包括设置在电源端子与电路点之间的MOS晶体管 处于电位并且在高电位和电路点之间的电位范围内工作，并且用于使电路上的电位与第一MOS晶体管的源极处的电位一致的电路。

    Nonvolatile semiconductor memory device
    49.
    发明授权
    Nonvolatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US4395724A

    公开(公告)日：1983-07-26

    申请号：US180435

    申请日：1980-08-22

    申请人： Hiroshi Iwahashi ,  Masamichi Asano

    发明人： Hiroshi Iwahashi ,  Masamichi Asano

    IPC分类号： H01L27/112 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78 ,  H01L27/02

    CPC分类号： H01L29/7881

    摘要： In a nonvolatile semiconductor memory device using as memory cells insulated-gate type field effect transistors each having source and drain regions, a floating gate electrode, and a control gate electrode, the width of the floating and control gate electrodes is narrower at those portions which are located over a channel between the source and drain regions in each memory cell than at those portions which are not located over the channel.

    摘要翻译： 在使用各自具有源极和漏极区域的存储单元绝缘栅型场效应晶体管的非易失性半导体存储器件中，浮置栅极电极和控制栅电极，浮动栅极电极和控制栅电极的宽度在 位于每个存储器单元中的源极和漏极区域之间的通道上，而不是位于通道上方的那些部分。

    Memory device utilizing MOS FETs
    50.
    发明授权
    Memory device utilizing MOS FETs 失效
    使用MOS FET的存储器件

    公开(公告)号：US4340943A

    公开(公告)日：1982-07-20

    申请号：US153951

    申请日：1980-05-28

    申请人： Masamichi Asano ,  Hiroshi Iwahashi

    发明人： Masamichi Asano ,  Hiroshi Iwahashi

    IPC分类号： G11C7/12 ,  G11C11/34 ,  G11C11/408 ,  G11C11/417 ,  G11C16/04 ,  G11C16/24 ,  G11C7/00 ,  G11C11/40

    CPC分类号： G11C16/0416 ,  G11C11/4085 ,  G11C11/417 ,  G11C16/24 ,  G11C7/12

    摘要： A memory device utilizing metal oxide semiconductor field effect transistors (MOS FETs) formed in a semiconductor substrate. The memory device is so improved as to be accessed without a delay and as not to behave erroneously, in spite of a potential variation of data line or the semiconductor substrate. It comprises a plurality of row lines for supplying input signals, a plurality of column lines for supplying output signals, decoders for selecting any one of these lines, a plurality of memory cells connected to the row and column lines in a specific manner, a voltage sensing circuit connected to the column lines, a first potential source connected to the column lines, a second potential source for supplying the memory cells with a source voltage, and means for holding the column lines at a potential substantially equal to the voltage supplied from the second potential source when the potential of the column lines or the substrate varies.

    摘要翻译： 一种利用形成在半导体衬底中的金属氧化物半导体场效应晶体管（MOS FET）的存储器件。 尽管存在数据线或半导体衬底的潜在变化，存储器件如此改进以便无延迟地被访问并且不会出错。 它包括用于提供输入信号的多条行线，用于提供输出信号的多条列线，用于选择这些线中的任何一条的解码器，以特定方式连接到行和列线的多个存储单元，电压 连接到列线的感测电路，连接到列线的第一电位源，用于向存储器单元提供源极电压的第二电位源，以及用于将列线保持在基本上等于从 当列线或衬底的电位变化时，第二电位源。