摘要:
An MOS device comprising a gate dielectric formed on a first conductivity type region. A gate electrode formed on the gate dielectric. A pair of sidewall spacers are formed along laterally opposite sidewalls of the gate electrode. A pair of deposited silicon or silicon alloy source/drain regions are formed in the first conductivity region and on opposite sides of a gate electrode wherein the silicon or silicon alloy source/drain regions extend beneath the gate electrode and to define a channel region beneath the gate electrode in the first conductivity type region wherein the channel region directly beneath the gate electrode is larger than the channel region deeper into said first conductivity type region.
摘要:
A semiconductor device and an improved method for making it are described. The semiconductor device comprises a dual damascene interconnect that includes a conductive line. The device further includes a support structure that is spaced from the conductive line, and an insulating layer that is formed on the support structure and the conductive line. In the method for forming that device, a support structure is formed on a substrate, and an insulating layer is formed adjacent to it. Portions of the insulating layer are removed to form a via and a trench, which are filled with a conductive material to generate a dual damascene interconnect that includes a conductive line, wherein the conductive line is spaced from the support structure.
摘要:
Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics. Alternative embodiments can be implemented with a back filled recess of a single conductivity type.
摘要:
A die assembly formed on a thin dielectric sheet is described. In one example, a first and a second die have interconnect areas. A dielectric sheet, such as glass, silicon, or oxidized metal is applied over the interconnect areas of dies. Conductive vias are formed in the dielectric sheet to connect with pads of the interconnect areas. A build-up layer includes routing to connect pads of the first die interconnect area to pads of the second die interconnect area through the conductive vias and a cover is applied over the dies, the dielectric sheet, and the build-up layer.
摘要:
A conveyor system is disclosed herein. An embodiment of the conveyor system comprises a first end, a second end, a first side, and a second side. A belt extends between the first end and the second end. The belt has a belt first side located proximate the first side of the conveyor. A first magnetic force acts on the belt first side relative to the first side of the conveyor.
摘要:
According to one embodiment a method is disclosed. The method includes applying a photoresist layer to a first wafer, etching the first wafer, bonding the first wafer to a second wafer and thinning the first wafer; wherein an unsupported bevel portion of the first wafer is removed.
摘要:
An improved method for making a semiconductor device is described. Initially, a structure is formed that includes first and second hard masking layers that cover a dielectric layer. A layer of photoresist is deposited and patterned to expose part of the second hard masking layer to define a via. That exposed part of the second hard masking layer is then etched. A second layer of photoresist is deposited and patterned to expose a second part of the second hard masking layer to define a trench. After etching the exposed second part of the second hard masking layer, a via and trench are etched into the dielectric layer, which are then filled with a conductive material.
摘要:
Methods and structures formed thereby are described, of forming self-aligned contact structures for microelectronic devices. An embodiment includes forming a trench in a source/drain region of a transistor device disposed in a device layer, wherein the device layer is on a substrate, forming a fill material in the trench, forming a source/drain material on the fill material, forming a first source/drain contact on a first side of the source/drain material, and then forming a second source drain contact on a second side of the source/drain material.
摘要:
Disclosed are embodiments of a substrate for an integrated circuit (IC) device. The substrate includes a core comprised of two or more discrete glass layers that have been bonded together. A separate bonding layer may be disposed between adjacent glass layers to couple these layers together. The substrate may also include build-up structures on opposing sides of the multi-layer glass core, or perhaps on one side of the core. Electrically conductive terminals may be formed on both sides of the substrate, and an IC die may be coupled with the terminals on one side of the substrate. The terminals on the opposing side may be coupled with a next-level component, such as a circuit board. One or more conductors extend through the multi-layer glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the core. Other embodiments are described and claimed.
摘要:
Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics. Alternative embodiments can be implemented with a back filled recess of a single conductivity type.