公开(公告)号：US09805986B2

公开(公告)日：2017-10-31

申请号：US15079414

申请日：2016-03-24

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  Manoj Mehrotra ,  Rick L. Wise

IPC: H01L21/84 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/161 ,  H01L29/20

CPC classification number: H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0684 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20

Abstract: An integrated circuit containing an n-channel finFET and a p-channel finFET has a dielectric layer over a silicon substrate. The fins of the finFETs have semiconductor materials with higher mobilities than silicon. A fin of the n-channel finFET is on a first silicon-germanium buffer in a first trench through the dielectric layer on the substrate. A fin of the p-channel finFET is on a second silicon-germanium buffer in a second trench through the dielectric layer on the substrate. The fins extend at least 10 nanometers above the dielectric layer. The fins are formed by epitaxial growth on the silicon-germanium buffers in the trenches in the dielectric layer, followed by CMP planarization down to the dielectric layer. The dielectric layer is recessed to expose the fins. The fins may be formed concurrently or separately.

公开(公告)号：US09780192B2

公开(公告)日：2017-10-03

申请号：US15093881

申请日：2016-04-08

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  Mahalingam Nandakumar

IPC: H01L29/66 ,  H01L29/51 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/321 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/49 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L21/32

CPC classification number: H01L29/66545 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/0228 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28123 ,  H01L21/28167 ,  H01L21/28194 ,  H01L21/28238 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/32 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/823456 ,  H01L21/823468 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/42368 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66553 ,  H01L29/7833

Abstract: A replacement metal gate transistor structure and method with thin silicon nitride sidewalls and with little or no high-k dielectric on the vertical sidewalls of the replacement gate transistor trench.

公开(公告)号：US09721847B2

公开(公告)日：2017-08-01

申请号：US14724185

申请日：2015-05-28

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  Brian K. Kirkpatrick

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/8238 ,  H01L21/28 ,  H01L21/324 ,  H01L21/3213 ,  H01L21/477 ,  H01L29/66 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L21/82385 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/32131 ,  H01L21/32133 ,  H01L21/32134 ,  H01L21/324 ,  H01L21/477 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: An integrated circuit with a thick TiN metal gate with a work function greater than 4.85 eV and with a thin TiN metal gate with a work function less than 4.25 eV. An integrated circuit with a replacement gate PMOS TiN metal gate transistor with a workfunction greater than 4.85 eV and with a replacement gate NMOS TiN metal gate transistor with a workfunction less than 4.25 eV. An integrated circuit with a gate first PMOS TiN metal gate transistor with a workfunction greater than 4.85 eV and with a gate first NMOS TiN metal gate transistor with a workfunction less than 4.25 eV.

公开(公告)号：US09496262B2

公开(公告)日：2016-11-15

申请号：US14572949

申请日：2014-12-17

Applicant: Texas Instruments Incorporated

Inventor： Manoj Mehrotra ,  Charles Frank Machala, III ,  Rick L. Wise ,  Hiroaki Niimi

IPC: H01L21/02 ,  H01L21/70 ,  H01L21/8238 ,  H01L21/20 ,  H01L21/36 ,  H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20

Abstract: An integrated circuit containing an n-channel finFET and a p-channel finFET is formed by forming a first polarity fin epitaxial layer for a first polarity finFET, and subsequently forming a hard mask which exposes an area for a second, opposite, polarity fin epitaxial layer for a second polarity finFET. The second polarity fin epitaxial layer is formed in the area exposed by the hard mask. A fin mask defines the first polarity fin and second polarity fin areas, and a subsequent fin etch forms the respective fins. A layer of isolation dielectric material is formed over the substrate and fins. The layer of isolation dielectric material is planarized down to the fins. The layer of isolation dielectric material is recessed so that the fins extend at least 10 nanometers above the layer of isolation dielectric material. Gate dielectric layers and gates are formed over the fins.

Abstract translation: 通过形成用于第一极性finFET的第一极性鳍外延层形成包含n沟道finFET和p沟道finFET的集成电路，随后形成暴露第二相反极性鳍片外延区域的硬掩模 层用于第二极性finFET。 在由硬掩模暴露的区域中形成第二极性鳍外延层。 翅片掩模限定第一极性鳍片和第二极性鳍片区域，并且随后的鳍片蚀刻形成相应的鳍片。 隔离介质材料层形成在衬底和鳍片之上。 隔离绝缘材料层被平坦化到鳍片。 隔离电介质材料层是凹进的，使得翅片在隔离介电材料层之上延伸至少10纳米。 栅极电介质层和栅极形成在鳍片上。

公开(公告)号：US09337046B1

公开(公告)日：2016-05-10

申请号：US15003466

申请日：2016-01-21

Applicant: Texas Instruments Incorporated

Inventor： Malcolm J. Bevan ,  Haowen Bu ,  Hiroaki Niimi ,  Husam N. Alshareef

IPC: H01L21/28 ,  H01L29/51

CPC classification number: H01L21/28158 ,  C23C16/45557 ,  C23C16/4582 ,  H01J37/32752 ,  H01J37/32825 ,  H01J37/32899 ,  H01J2237/3321 ,  H01L21/02181 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02318 ,  H01L21/02323 ,  H01L21/02326 ,  H01L21/02329 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28035 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28229 ,  H01L21/3105 ,  H01L21/31604 ,  H01L21/318 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/67161 ,  H01L21/67167 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/6776 ,  H01L29/42364 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/78

Abstract: Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.

公开(公告)号：US09324717B2

公开(公告)日：2016-04-26

申请号：US14573021

申请日：2014-12-17

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  Manoj Mehrotra ,  Rick L. Wise

IPC: H01L21/84 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0684 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20

Abstract: An integrated circuit containing an n-channel finFET and a p-channel finFET has a dielectric layer over a silicon substrate. The fins of the finFETs have semiconductor materials with higher mobilities than silicon. A fin of the n-channel finFET is on a first silicon-germanium buffer in a first trench through the dielectric layer on the substrate. A fin of the p-channel finFET is on a second silicon-germanium buffer in a second trench through the dielectric layer on the substrate. The fins extend at least 10 nanometers above the dielectric layer. The fins are formed by epitaxial growth on the silicon-germanium buffers in the trenches in the dielectric layer, followed by CMP planarization down to the dielectric layer. The dielectric layer is recessed to expose the fins. The fins may be formed concurrently or separately.

Abstract translation: 包含n沟道finFET和p沟道finFET的集成电路在硅衬底上具有介电层。 finFET的鳍片具有比硅更高的迁移率的半导体材料。 n沟道finFET的鳍在通过衬底上的电介质层的第一沟槽中的第一硅 - 锗缓冲器上。 p沟道finFET的鳍在通过衬底上的电介质层的第二沟槽中的第二硅 - 锗缓冲器上。 翅片延伸至介电层上方至少10纳米。 散热片通过外延生长在电介质层的沟槽中的硅 - 锗缓冲器上形成，随后CMP平坦化到介电层。 电介质层凹入以暴露翅片。 翅片可以同时或分开地形成。

公开(公告)号：US20150187659A1

公开(公告)日：2015-07-02

申请号：US14575490

申请日：2014-12-18

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Hiroaki Niimi

IPC: H01L21/8238 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L21/823857 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28202 ,  H01L21/28238 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/82385 ,  H01L27/0922 ,  H01L29/66545 ,  H01L29/6659

Abstract: A replacement metal gate transistor is formed with high quality gate dielectric under the high-k dielectric. The high quality gate dielectric is formed on the substrate at a temperature of at least 850° C. A sacrificial gate dielectric is formed on the high quality gate dielectric and a polysilicon replacement gate is formed on the sacrificial gate dielectric. The polysilicon replacement gate is removed leaving a gate trench. The sacrificial gate dielectric is removed from a bottom of the gate. A high-k dielectric is deposited into the gate trench. Metal gate material is deposited on the high-k dielectric.

Abstract translation: 在高k电介质下形成具有高质量栅极电介质的替代金属栅极晶体管。 在至少850℃的温度下在衬底上形成高质量的栅极电介质。在高质量栅极电介质上形成牺牲栅极电介质，并且在牺牲栅极电介质上形成多晶硅替代栅极。 去除多晶硅替代栅极留下栅极沟槽。 从栅极的底部去除牺牲栅极电介质。 高k电介质沉积到栅极沟槽中。 金属栅极材料沉积在高k电介质上。

公开(公告)号：US20150187653A1

公开(公告)日：2015-07-02

申请号：US14567507

申请日：2014-12-11

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  Brian K. Kirkpatrick

IPC: H01L21/8238 ,  H01L21/28

CPC classification number: H01L21/82385 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/32131 ,  H01L21/32133 ,  H01L21/32134 ,  H01L21/324 ,  H01L21/477 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: An integrated circuit with a thick TiN metal gate with a work function greater than 4.85 eV and with a thin TiN metal gate with a work function less than 4.25 eV. An integrated circuit with a replacement gate PMOS TiN metal gate transistor with a workfunction greater than 4.85 eV and with a replacement gate NMOS TiN metal gate transistor with a workfunction less than 4.25 eV. An integrated circuit with a gate first PMOS TiN metal gate transistor with a workfunction greater than 4.85 eV and with a gate first NMOS TiN metal gate transistor with a workfunction less than 4.25 eV.

公开(公告)号：US20150179783A1

公开(公告)日：2015-06-25

申请号：US14635288

申请日：2015-03-02

Applicant: Texas Instruments Incorporated

Inventor： Manoj Mehrotra ,  Hiroaki Niimi

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/06

CPC classification number: H01L29/78 ,  H01L21/28114 ,  H01L29/0653 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: The gate-to-source and gate-to-drain overlap capacitance of a MOS transistor with a metal gate and a high-k gate dielectric are reduced by forming the high-k gate dielectric along the inside of a sidewall structure which has been formed to lie further away from the source and the drain.

Abstract translation: 通过沿着形成的侧壁结构的内部形成高k栅极电介质来减小具有金属栅极和高k栅极电介质的MOS晶体管的栅极到源极和栅极到漏极的重叠电容 远离源头和排水沟。

公开(公告)号：US09054056B2

公开(公告)日：2015-06-09

申请号：US14451489

申请日：2014-08-05

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  Jarvis Benjamin Jacobs ,  Ajith Varghese

IPC: H01L21/469 ,  H01L21/324 ,  H01L21/265 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L21/324 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/823412 ,  H01L21/823462 ,  H01L29/105 ,  H01L29/66477

Abstract: A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation.

Abstract translation: 两步热处理方法包括在半导体器件的硅衬底中进行离子注入。 在半导体器件上执行第一热处理程序。 在半导体器件上连续执行第二热处理程序以减少由离子注入产生的损伤。