公开(公告)号：US20060216948A1

公开(公告)日：2006-09-28

申请号：US10547504

申请日：2004-03-04

申请人： Tadahiro Ohmi ,  Akinobu Teramoto

发明人： Tadahiro Ohmi ,  Akinobu Teramoto

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/02052 ,  H01L21/67017 ,  H01L21/67028 ,  H01L21/67034 ,  H01L21/6704 ,  H01L21/67046 ,  H01L21/67051 ,  H01L21/6715 ,  H01L21/67161 ,  H01L21/67173

摘要： An object of the present invention is to completely remove water adhering to a substrate due to cleaning and carry the substrate with the water being removed, to a film forming unit. The present invention is a substrate processing system including: a cleaning unit for cleaning a substrate with a cleaning solution; a water removing unit for removing water adhering to the substrate cleaned in the cleaning unit; and a carrier section for carrying the substrate from which water has been removed in the water removing unit to another substrate processing unit through a dry atmosphere.

摘要翻译： 本发明的一个目的是完全去除由于清洗而附着在基材上的水，并且将被除去的水携带在基板上的成膜单元。 本发明是一种基板处理系统，包括：用清洗液清洗基板的清洗单元; 除水单元，用于去除在清洁单元中清洁的粘附到基底上的水; 以及承载部，其通过干燥气氛将去除水分中的水从基板移出到另一基板处理单元。

公开(公告)号：US20060180840A1

公开(公告)日：2006-08-17

申请号：US10560397

申请日：2004-06-11

申请人： Takefumi Nishimuta ,  Hiroshi Miyagi ,  Tadahiro Ohmi ,  Shigetoshi Sugawa ,  Akinobu Teramoto

发明人： Takefumi Nishimuta ,  Hiroshi Miyagi ,  Tadahiro Ohmi ,  Shigetoshi Sugawa ,  Akinobu Teramoto

IPC分类号： H01L29/94 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L29/66787 ,  H01L21/823807 ,  H01L21/82385 ,  H01L27/092

摘要： A rectangular parallelepiped projecting portion (21) having a height of HB and a width of WB is formed on a silicon substrate, and a gate oxide film is formed on a part of the top surface and the side surface of the projecting portion (21), thereby generating a MOS transistor. By connecting in parallel a p-channel MOS transistor and an n-channel MOS transistor produced as described above, a switch of a switched capacitor circuit is configured, thereby reducing a leak current and a DC offset of the switched capacitor circuit.

摘要翻译： 在硅衬底上形成具有H B高度和W B B的宽度的长方体的突出部分（21），并且栅极氧化膜形成在 突出部分（21）的顶表面和侧表面的一部分，从而产生MOS晶体管。 通过并联连接如上所述制造的p沟道MOS晶体管和n沟道MOS晶体管，构造开关电容器电路的开关，从而减小开关电容器电路的漏电流和DC偏移。

公开(公告)号：US08895410B2

公开(公告)日：2014-11-25

申请号：US11991908

申请日：2005-09-13

申请人： Tadahiro Ohmi ,  Akinobu Teramoto ,  Hiroshi Akahori

发明人： Tadahiro Ohmi ,  Akinobu Teramoto ,  Hiroshi Akahori

IPC分类号： H01L21/322 ,  H01L21/223 ,  H01L21/30 ,  H01L29/78 ,  H01L29/66 ,  H01L21/31

CPC分类号： H01L21/3003 ,  B65G2201/0247 ,  H01L21/31 ,  H01L29/6659 ,  H01L29/7833

摘要： A cause of deteriorating the hydrogen termination on the surface of a wafer is found to be water adsorbed on the surface. By exposing the wafer to an inert gas atmosphere containing an H2 gas so as to suppress the oxidation reaction due to the water, it is possible to improve the hydrogen termination on the wafer surface.

摘要翻译： 发现晶片表面的氢终止劣化的原因是水被吸附在表面上。 通过将晶片暴露于含有H 2气体的惰性气体气氛中以抑制由于水引起的氧化反应，可以改善晶片表面上的氢终止。

公开(公告)号：US08643106B2

公开(公告)日：2014-02-04

申请号：US12308846

申请日：2007-06-21

申请人： Tadahiro Ohmi ,  Akinobu Teramoto ,  Cheng Weitao

发明人： Tadahiro Ohmi ,  Akinobu Teramoto ,  Cheng Weitao

IPC分类号： H01L27/12

CPC分类号： H01L29/78654 ,  H01L29/78603 ,  H01L29/78648

摘要： A transistor capable of adjusting a threshold value is obtained by adjusting an impurity concentration of a silicon substrate supporting an SOI layer and by controlling a thickness of a buried insulating layer formed on a surface of the silicon substrate in contact with the SOI layer.

摘要翻译： 通过调整支撑SOI层的硅衬底的杂质浓度，并且通过控制形成在与SOI层接触的硅衬底表面上的掩埋绝缘层的厚度来获得能够调节阈值的晶体管。

公开(公告)号：US08633395B2

公开(公告)日：2014-01-21

申请号：US12995514

申请日：2009-05-22

申请人： Tadahiro Ohmi ,  Shigetoshi Sugawa ,  Hiroshi Imai ,  Akinobu Teramoto

发明人： Tadahiro Ohmi ,  Shigetoshi Sugawa ,  Hiroshi Imai ,  Akinobu Teramoto

IPC分类号： H05K1/03 ,  H05K1/11

CPC分类号： H05K1/0218 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2223/6688 ,  H01L2924/0002 ,  H01L2924/19032 ,  H01L2924/3011 ,  H05K1/025 ,  H05K1/0265 ,  H05K3/4652 ,  H05K2201/0191 ,  H05K2201/0352 ,  H05K2201/0715 ,  H05K2201/096 ,  H05K2201/09618 ,  H05K2201/09727 ,  H05K2201/09972 ,  H01L2924/00

摘要： A multilayer wiring board 100 comprises a first wiring region 101 where wirings 103a and insulating layers 104a and 104b are alternately laminated, and a second wiring region 102 where a thickness H2 of an insulating layer 104 is twice or more a thickness H1 of the insulating layer in the first wiring region 101 and a width W2 of a wiring 103b is twice or more a width W1 of the wiring in the first wiring region 101. The first wiring region 101 and the second wiring region 102 are integrally formed on the same board.

摘要翻译： 多层布线基板100包括：布线103a和绝缘层104a，104b交替层叠的第一布线区域101和绝缘层104的厚度H2为绝缘层的厚度H1的两倍以上的第二布线区域102 在第一布线区域101中，布线103b的宽度W2是第一布线区域101中的布线的宽度W1的两倍或更多倍。第一布线区域101和第二布线区域102一体地形成在同一个板上。

公开(公告)号：US20130292700A1

公开(公告)日：2013-11-07

申请号：US13981048

申请日：2012-01-23

申请人： Akinobu Teramoto ,  Hiroshi Kambayashi ,  Hirokazu Ueda ,  Yuichiro Morozumi ,  Katsushige Harada ,  Kazuhide Hasebe ,  Tadahiro Ohmi

发明人： Akinobu Teramoto ,  Hiroshi Kambayashi ,  Hirokazu Ueda ,  Yuichiro Morozumi ,  Katsushige Harada ,  Kazuhide Hasebe ,  Tadahiro Ohmi

IPC分类号： H01L29/20 ,  H01L21/02

CPC分类号： H01L21/02274 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/0254 ,  H01L21/28264 ,  H01L23/564 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42364 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating a semiconductor device including GaN (gallium nitride) that composes a semiconductor layer and includes forming a gate insulating film, in which at least one film selected from the group of a SiO2 film and an Al2O3 film is formed on a nitride layer containing GaN by using microwave plasma and the formed film is used as at least a part of the gate insulating film.

摘要翻译： 一种制造半导体器件的方法，该半导体器件包括构成半导体层并包括形成栅极绝缘膜的GaN（氮化镓），其中在氮化物层上形成选自SiO 2膜和Al 2 O 3膜中的至少一种膜 通过使用微波等离子体形成含GaN的GaN，并且将形成的膜用作栅极绝缘膜的至少一部分。

公开(公告)号：US20130032819A1

公开(公告)日：2013-02-07

申请号：US13582229

申请日：2011-03-02

申请人： Hiroshi Kambayashi ,  Katsunori Ueno ,  Takehiko Nomura ,  Yoshihiro Sato ,  Akinobu Teramoto ,  Tadahiro Ohmi

发明人： Hiroshi Kambayashi ,  Katsunori Ueno ,  Takehiko Nomura ,  Yoshihiro Sato ,  Akinobu Teramoto ,  Tadahiro Ohmi

IPC分类号： H01L29/51

CPC分类号： H01L21/28264 ,  C23C16/403 ,  C23C16/4488 ,  H01L21/02178 ,  H01L21/02277 ,  H01L29/2003 ,  H01L29/513 ,  H01L29/517 ,  H01L29/78

摘要： The semiconductor transistor according the present invention includes an active layer composed of a GaN-based semiconductor and a gate insulating film formed on the active layer. The gate insulating film has a first insulating film including one or more compounds selected from the group consisting of Al2O3, HfO2, ZrO2, La2O3, and Y2O3 formed on the active layer, and a second insulating film composed of SiO2 formed on the first insulating film.

摘要翻译： 根据本发明的半导体晶体管包括由有源层形成的GaN基半导体和栅极绝缘膜构成的有源层。 栅极绝缘膜具有包含一种或多种选自Al 2 O 3，HfO 2，ZrO 2，La 2 O 3和Y 2 O 3的化合物的第一绝缘膜和形成在第一绝缘膜上的由SiO 2构成的第二绝缘膜 。

公开(公告)号：US08314449B2

公开(公告)日：2012-11-20

申请号：US12604015

申请日：2009-10-22

申请人： Takefumi Nishimuta ,  Hiroshi Miyagi ,  Tadahiro Ohmi ,  Shigetoshi Sugawa ,  Akinobu Teramoto

发明人： Takefumi Nishimuta ,  Hiroshi Miyagi ,  Tadahiro Ohmi ,  Shigetoshi Sugawa ,  Akinobu Teramoto

IPC分类号： H01L21/76

CPC分类号： H01L29/7851 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/82385 ,  H01L29/045

摘要： A MIS transistor, formed on a semiconductor substrate, assumed to comprise a semiconductor substrate (702, 910) comprising a projecting part (704, 910B) with at least two different crystal planes on the surface on a principal plane, a gate insulator (708, 920B) for covering at least a part of each of said at least two different crystal planes constituting the surface of the projecting part, a gate electrode (706, 930B), comprised on each of said at least two different crystal planes constituting the surface of the projecting part, which sandwiches the gate insulator with the said at least two different planes, and a single conductivity type diffusion region (710a, 710b, 910c, 910d) formed in the projecting part facing each of said at least two different crystal planes and individually formed on both sides of the gate electrode. Such a configuration allows control over increase in the element area and increase of channel width.

摘要翻译： 形成在半导体衬底上的MIS晶体管被假设为包括半导体衬底（702,910），该半导体衬底包括在主平面上的表面上具有至少两个不同晶面的突出部分（704,910B），栅极绝缘体（708 ，920B），用于覆盖构成所述突出部分的表面的所述至少两个不同晶面的每一个的至少一部分;栅电极（706,930B），包括在构成所述表面的所述至少两个不同晶面中的每一个上 所述突出部分与所述至少两个不同平面夹住所述栅极绝缘体，以及形成在所述突出部分中的所述至少两个不同晶面中的每一个的单导电型扩散区域（710a，710b，910c，910d） 并分别形成在栅电极的两侧。 这种配置允许控制元件面积的增加和通道宽度的增加。

公开(公告)号：US20120208375A1

公开(公告)日：2012-08-16

申请号：US13453206

申请日：2012-04-23

申请人： Tadahiro Ohmi ,  Shigetoshi Sugawa ,  Akinobu Teramoto ,  Hiroshi Akahori ,  Keiichi Nii

发明人： Tadahiro Ohmi ,  Shigetoshi Sugawa ,  Akinobu Teramoto ,  Hiroshi Akahori ,  Keiichi Nii

IPC分类号： H01L21/316 ,  H01L21/314

CPC分类号： H01L21/3185 ,  H01L21/0214 ,  H01L21/02142 ,  H01L21/02164 ,  H01L21/02175 ,  H01L21/02238 ,  H01L21/02271 ,  H01L21/02301 ,  H01L21/30604 ,  H01L21/31654 ,  H01L21/318 ,  H01L29/6659

摘要： In a semiconductor device formed on a silicon surface which has a substantial (110) crystal plane orientation, the silicon surface is flattened so that an arithmetical mean deviation of surface Ra is not greater than 0.15 nm, preferably, 0.09 nm, which enables to manufacture an n-MOS transistor of a high mobility. Such a flattened silicon surface is obtained by repeating a deposition process of a self-sacrifice oxide film in an oxygen radical atmosphere and a removing process of the self-sacrifice oxide film, by cleaning the silicon surface in deaerated H2O or a low OH density atmosphere, or by strongly terminating the silicon surface by hydrogen or heavy hydrogen. The deposition process of the self-sacrifice oxide film may be carried out by isotropic oxidation.

摘要翻译： 在形成在具有大致（110）晶面取向的硅表面上的半导体器件中，硅表面变平，使得表面Ra的算术平均偏差不大于0.15nm，优选为0.09nm，这使得能够制造 高迁移率的n-MOS晶体管。 通过在脱氧H 2 O或低OH密度气氛中清洗硅表面，通过在氧自由基气氛中重复自牺牲氧化物膜的沉积工艺和自牺牲氧化物膜的去除工艺来获得这种扁平化的硅表面 ，或通过氢或重氢强烈地终止硅表面。 自牺牲氧化膜的沉积工艺可以通过各向同性氧化进行。

公开(公告)号：US08134376B2

公开(公告)日：2012-03-13

申请号：US11795247

申请日：2006-01-17

申请人： Tadahiro Ohmi ,  Akinobu Teramoto

发明人： Tadahiro Ohmi ,  Akinobu Teramoto

IPC分类号： G01R27/08

CPC分类号： G01R31/2621 ,  G01R27/2605

摘要： In a method for measuring an electronic device which is an object to be measured, a passive element is connected to the electronic device in parallel, and electric parameters of the electronic device are extracted by measuring an impedance of the entire circuit.

摘要翻译： 在作为测量对象的电子设备的测量方法中，无源元件并联连接到电子设备，并且通过测量整个电路的阻抗来提取电子设备的电参数。