公开(公告)号：US11728376B2

公开(公告)日：2023-08-15

申请号：US17445692

申请日：2021-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Lin ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L29/06 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0607 ,  H01L21/28264 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7848

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer.

公开(公告)号：US20230154896A1

公开(公告)日：2023-05-18

申请号：US18149509

申请日：2023-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Tse Chen ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Hui-Min Huang ,  Hsuan-Ting Kuo ,  Ming-Da Cheng

IPC: H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L21/768 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/568 ,  H01L25/50 ,  H01L21/565 ,  H01L21/76804 ,  H01L21/7684 ,  H01L21/76883 ,  H01L25/0652 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/06524 ,  H01L2224/18 ,  H01L2224/04105 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/12105

Abstract: An embodiment is method including forming a first die package over a carrier substrate, the first die package comprising a first die, forming a first redistribution layer over and coupled to the first die, the first redistribution layer including one or more metal layers disposed in one or more dielectric layers, adhering a second die over the redistribution layer, laminating a first dielectric material over the second die and the first redistribution layer, forming first vias through the first dielectric material to the second die and forming second vias through the first dielectric material to the first redistribution layer, and forming a second redistribution layer over the first dielectric material and over and coupled to the first vias and the second vias.

公开(公告)号：US20230154764A1

公开(公告)日：2023-05-18

申请号：US17655645

申请日：2022-03-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Sung Huang ,  Tsung-Hsien Chiang ,  Ming Hung Tseng ,  Hao-Yi Tsai ,  Yu-Hsiang Hu ,  Chih-Wei Lin ,  Lipu Kris Chuang ,  Wei Lun Tsai ,  Kai-Ming Chiang ,  Ching Yao Lin ,  Chao-Wei Li ,  Ching-Hua Hsieh

IPC: H01L21/48 ,  H01L23/498

CPC classification number: H01L21/4857 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/32

Abstract: A method includes forming a first metal mesh over a carrier, forming a first dielectric layer over the first metal mesh, and forming a second metal mesh over the first dielectric layer. The first metal mesh and the second metal mesh are staggered. The method further includes forming a second dielectric layer over the second metal mesh, attaching a device die over the second dielectric layer, with the device die overlapping the first metal mesh and the second metal mesh, encapsulating the device die in an encapsulant, and forming redistribution lines over and electrically connecting to the device die.

公开(公告)号：US11626339B2

公开(公告)日：2023-04-11

申请号：US17201856

申请日：2021-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Sung Huang ,  Ming Hung Tseng ,  Yen-Liang Lin ,  Hao-Yi Tsai ,  Chi-Ming Tsai ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Ming-Che Ho

IPC: H01L23/31 ,  H01L23/16 ,  H01L23/522 ,  H01L21/768 ,  H01L21/56 ,  H01L23/528

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

公开(公告)号：US20230072507A1

公开(公告)日：2023-03-09

申请号：US18055241

申请日：2022-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih Wei Bih ,  Sheng-Wei Yeh ,  Yen-Yu Chen ,  Wen-Hao Cheng ,  Chih-Wei Lin ,  Chun-Chih Lin

IPC: H01L23/00 ,  H01L21/02

Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.

公开(公告)号：US20220013422A1

公开(公告)日：2022-01-13

申请号：US16924208

申请日：2020-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mao-Yen Chang ,  Chih-Wei Lin ,  Hao-Yi Tsai ,  Kuo-Lung Pan ,  Chun-Cheng Lin ,  Tin-Hao Kuo ,  Yu-Chia Lai ,  Chih-Hsuan Tai

IPC: H01L23/31 ,  H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/40 ,  H01L23/538 ,  H01L23/498 ,  H01L25/00

Abstract: Provided is a package structure including a composite wafer, a plurality of dies, an underfill, and a plurality of dam structures. The composite wafer has a first surface and a second surface opposite to each other. The composite wafer includes a plurality of seal rings dividing the composite wafer into a plurality of packages; and a plurality of through holes respectively disposed between the seal rings and penetrating through the first and second surfaces. The dies are respectively bonded onto the packages at the first surface by a plurality of connectors. The underfill laterally encapsulates the connectors. The dam structures are disposed on the first surface of the composite wafer to separate the underfill from the through holes.

公开(公告)号：US11177156B2

公开(公告)日：2021-11-16

申请号：US16547605

申请日：2019-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chieh Yang ,  Shing-Chao Chen ,  Ching-Hua Hsieh ,  Chih-Wei Lin

IPC: H01L21/683 ,  H01L21/82 ,  H01L21/56 ,  H01L23/00

Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor wafer having an active side and a back side opposite to the active side is provided. A plurality of conductive bumps are provided on the active side. A protection film is laminated on the active side, wherein the protection film includes a dielectric film covering the plurality of conductive bumps and a cover film covering the dielectric film. A thinning process is performed on the back side to form a thinned semiconductor wafer. The cover film is removed from the dielectric film. A singularization process is performed on the thinned semiconductor wafer with the dielectric film to form a plurality of semiconductor devices.

公开(公告)号：US11088124B2

公开(公告)日：2021-08-10

申请号：US16103925

申请日：2018-08-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shing-Chao Chen ,  Ching-Hua Hsieh ,  Chih-Wei Lin ,  Sheng-Chieh Yang

IPC: H01L23/31 ,  H01L25/16 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: A package includes a first redistribution structure, a bridge structure, an adhesive layer, a plurality of conductive pillars, an encapsulant, a first die, and a second die. The bridge structure is disposed on the first redistribution structure. The adhesive layer is disposed between the bridge structure and the first redistribution structure. The conductive pillars surround the bridge structure. A height of the conductive pillars is substantially equal to a sum of a height of the adhesive layer and a height of the bridge structure. The encapsulant encapsulates the bridge structure, the adhesive layer, and the conductive pillars. The first die and the second die are disposed over the bridge structure. The first die is electrically connected to the second die through the bridge structure. The first die and the second die are electrically connected to the first redistribution structure through the conductive pillars.

公开(公告)号：US20210091047A1

公开(公告)日：2021-03-25

申请号：US17113676

申请日：2020-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Tse Chen ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Hui-Min Huang ,  Hsuan-Ting Kuo ,  Ming-Da Cheng

IPC: H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L21/768 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

Abstract: An embodiment is method including forming a first die package over a carrier substrate, the first die package comprising a first die, forming a first redistribution layer over and coupled to the first die, the first redistribution layer including one or more metal layers disposed in one or more dielectric layers, adhering a second die over the redistribution layer, laminating a first dielectric material over the second die and the first redistribution layer, forming first vias through the first dielectric material to the second die and forming second vias through the first dielectric material to the first redistribution layer, and forming a second redistribution layer over the first dielectric material and over and coupled to the first vias and the second vias.

公开(公告)号：US10818614B2

公开(公告)日：2020-10-27

申请号：US16691512

申请日：2019-11-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Tse Chen ,  Ching-Hua Hsieh ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Hao-Cheng Hou ,  Jung-Wei Cheng

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L21/02

Abstract: A package structure including a semiconductor die, a warpage control layer, an insulating encapsulant and a redistribution layer is provided. The semiconductor die has an active surface and a backside surface opposite to the active surface. The warpage control layer is disposed on the backside surface of the semiconductor die, wherein the warpage control layer comprises a material having a Young's Modulus of 100 GPa or more. The insulating encapsulant is encapsulating the semiconductor die and the warpage control layer. The redistribution layer is located on the insulating encapsulant and over the active surface of the semiconductor die.