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    Redistribution layer structures for integrated circuit package
    41.
    发明授权
    Redistribution layer structures for integrated circuit package 有权

    公开(公告)号：US10665540B2

    公开(公告)日：2020-05-26

    申请号：US16520435

    申请日：2019-07-24

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jie Chen ,  Ying-Ju Chen ,  Hsien-Wei Chen ,  Der-Chyang Yeh ,  Chen-Hua Yu

    IPC: H01L23/528 ,  H01L23/00 ,  H01L25/10 ,  H01L23/522 ,  H01L25/00 ,  H01L25/065

    Abstract: A method of forming an integrated circuit (IC) package with improved performance and reliability is disclosed. The method includes forming a singulated IC die, coupling the singulated IC die to a carrier substrate, and forming a routing structure. The singulated IC die has a conductive via and the conductive via has a peripheral edge. The routing structure has a conductive structure coupled to the conductive via. The routing structure further includes a cap region overlapping an area of the conductive via, a routing region having a first width from a top-down view, and an intermediate region having a second width from the top-down view along the peripheral edge of the conductive via. The intermediate region is arranged to couple the cap region to the routing region and the second width is greater than the first width.

    THREE-DIMENSIONAL INTEGRATED CIRCUIT STRUCTURES
    42.
    发明申请
    THREE-DIMENSIONAL INTEGRATED CIRCUIT STRUCTURES 审中-公开

    公开(公告)号：US20200043861A1

    公开(公告)日：2020-02-06

    申请号：US16601588

    申请日：2019-10-15

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jie Chen ,  Hsien-Wei Chen ,  Ying-Ju Chen

    IPC: H01L23/544 ,  H01L25/065 ,  H01L23/528 ,  H01L23/522

    Abstract: Three-dimensional integrated circuit (3DIC) structures are disclosed. A 3DIC structure includes a first die and a second die bonded to the first die. The first die includes a first integrated circuit region and a first seal ring region around the first integrated circuit region, and has a first alignment mark within the first integrated circuit region. The second die includes a second integrated circuit region and a second seal ring region around the second integrated circuit region, and has a second alignment mark within the second seal ring region and corresponding to the first alignment mark.

    THREE-DIMENSIONAL INTEGRATED CIRCUIT STRUCTURES
    43.
    发明申请
    THREE-DIMENSIONAL INTEGRATED CIRCUIT STRUCTURES 审中-公开

    公开(公告)号：US20190393159A1

    公开(公告)日：2019-12-26

    申请号：US16016658

    申请日：2018-06-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jie Chen ,  Hsien-Wei Chen ,  Ying-Ju Chen

    IPC: H01L23/544 ,  H01L23/522 ,  H01L25/065 ,  H01L23/528

    Abstract: Three-dimensional integrated circuit (3DIC) structures are disclosed. A 3DIC structure includes a first die and a second die bonded to the first die. The first die includes a first integrated circuit region and a first seal ring region around the first integrated circuit region, and has a first alignment mark within the first integrated circuit region. The second die includes a second integrated circuit region and a second seal ring region around the second integrated circuit region, and has a second alignment mark within the second seal ring region and corresponding to the first alignment mark.

    Semiconductor structure
    44.
    发明授权
    Semiconductor structure 有权

    公开(公告)号：US10181449B1

    公开(公告)日：2019-01-15

    申请号：US15717971

    申请日：2017-09-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jie Chen ,  Hsien-Wei Chen ,  Ying-Ju Chen

    IPC: H01L23/00

    Abstract: A semiconductor structure including an insulating encapsulant, a first semiconductor die, a second semiconductor die and a redistribution circuit layer is provided. The first and the second semiconductor dies embedded in the insulating encapsulant and separated from one another. The first semiconductor die includes a first active surface accessibly exposed and a first conductive terminal distributed at the first active surface. The second semiconductor die includes a second active surface accessibly exposed and a second conductive terminal distributed at the second active surface. The redistribution circuit layer including a conductive trace is disposed on the first and the second active surfaces and the insulating encapsulant. The conductive trace is electrically connected from the first semiconductor die and meanderingly extends to the second semiconductor die, and a ratio of a total length of the conductive trace to the top width of the insulating encapsulant ranges from about 3 to about 10.

    Structure and method for forming integrated high density MIM capacitor
    45.
    发明授权
    Structure and method for forming integrated high density MIM capacitor 有权

    公开(公告)号：US12288802B2

    公开(公告)日：2025-04-29

    申请号：US18654658

    申请日：2024-05-03

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsien-Wei Chen ,  Ying-Ju Chen ,  Jie Chen ,  Ming-Fa Chen

    IPC: H01L23/522 ,  H01G4/30 ,  H01L21/768 ,  H01L49/02

    Abstract: Methods of forming a super high density metal-insulator-metal (SHDMIM) capacitor and semiconductor device are disclosed herein. A method includes depositing a first insulating layer over a semiconductor substrate and a series of conductive layers separated by a series of dielectric layers over the first insulating layer, the series of conductive layers including device electrodes and dummy metal plates. A first set of contact plugs through the series of conductive layers contacts one or more conductive layers of a first portion of the series of conductive layers. A second set of contact plugs through the series of dielectric layers avoids contact of a second portion of the series of conductive layers, the second portion of the series of conductive layers electrically floating.

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