公开(公告)号：US20240413230A1

公开(公告)日：2024-12-12

申请号：US18331305

申请日：2023-06-08

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Mu-Chieh Chang ,  Shu Ling Liao ,  Zhen-Cheng Wu ,  Sung-En Lin ,  Tze-Liang Lee

IPC: H01L29/775 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device includes: a substrate; a fin protruding above the substrate; a gate structure over the fin; source/drain regions over the fin and on opposing sides of the gate structure; channel layers over the fin and between the source/drain regions, where the gate structure wraps around the channel layers; and isolation structures under the source/drain regions, where the isolation structures separate the source/drain regions from the fin, where each of the isolation structures includes a liner layer and a dielectric layer over the liner layer, where the dielectric layer has a plurality of sublayers.

公开(公告)号：US12125911B2

公开(公告)日：2024-10-22

申请号：US17818595

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Han-Chi Lin ,  Chunyao Wang ,  Ching Yu Huang ,  Tze-Liang Lee ,  Yung-Chih Wang

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/3115 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/7843 ,  H01L21/0217 ,  H01L21/02208 ,  H01L21/0228 ,  H01L21/0234 ,  H01L21/3065 ,  H01L21/31155 ,  H01L21/32133 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method includes etching a first portion and a second portion of a dummy gate stack to form a first opening and a second opening, respectively, and depositing a silicon nitride layer to fill the first opening and the second opening. The deposition of the silicon nitride layer comprises a first process selected from treating the silicon nitride layer using hydrogen radicals, implanting the silicon nitride layer, and combinations thereof. The method further includes etching a third portion of the dummy gate stack to form a trench, etching a semiconductor fin underlying the third portion to extend the trench down into a bulk portion of a semiconductor substrate underlying the dummy gate stack, and depositing a second silicon nitride layer into the trench.

公开(公告)号：US12110587B2

公开(公告)日：2024-10-08

申请号：US17674977

申请日：2022-02-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tze-Liang Lee ,  Po-Hsien Cheng

IPC: H01J37/32 ,  C23C16/455

CPC classification number: C23C16/45536 ,  C23C16/45565 ,  H01J37/32211 ,  H01J37/3244 ,  H01J37/32522 ,  H01J37/32532 ,  H01J2237/2002 ,  H01J2237/332

Abstract: A deposition apparatus and a method are provided. A method includes placing a substrate over a platform in a chamber of a deposition system. A precursor material is introduced into the chamber. A first gas curtain is generated in front of a first electromagnetic (EM) radiation source coupled to the chamber. A plasma is generated from the precursor material in the chamber, wherein the plasma comprises dissociated components of the precursor material. The plasma is subjected to a first EM radiation from the first EM radiation source. The first EM radiation further dissociates the precursor material. A layer is deposited over the substrate. The layer includes a reaction product of the dissociated components of the precursor material.

公开(公告)号：US12087644B2

公开(公告)日：2024-09-10

申请号：US17493209

申请日：2021-10-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Hau Shiu ,  Ching-Yu Chang ,  Jei Ming Chen ,  Jr-Yu Chen ,  Tze-Liang Lee

IPC: H01L21/02 ,  H01L21/66

CPC classification number: H01L22/12 ,  H01L21/02186 ,  H01L21/0228

Abstract: In an embodiment, a method includes performing a first atomic layer deposition (ALD) process to form a first material layer over a first blank wafer, the first ALD process comprising: performing a first precursor sub-cycle using a first precursor; performing a first purge sub-cycle using a inert gas; and performing a second precursor sub-cycle using a second precursor and the inert gas; and performing a second purge sub-cycle for a first duration over a second blank wafer different from the first blank wafer using the inert gas to deposit first defects onto the second blank wafer.

公开(公告)号：US20240282571A1

公开(公告)日：2024-08-22

申请号：US18639575

申请日：2024-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Lin Tsai ,  Jung-Hau Shiu ,  Ching-Yu Chang ,  Jen Hung Wang ,  Shing-Chyang Pan ,  Tze-Liang Lee

IPC: H01L21/02 ,  C23C14/06 ,  C23C14/08 ,  C23C14/22 ,  C23C16/02 ,  C23C16/04 ,  C23C16/30 ,  C23C16/40 ,  C23C16/455 ,  H01J37/32 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/66

CPC classification number: H01L21/02126 ,  C23C14/0676 ,  C23C14/08 ,  C23C16/0245 ,  C23C16/042 ,  C23C16/045 ,  C23C16/308 ,  C23C16/401 ,  C23C16/45529 ,  C23C16/45536 ,  C23C16/45553 ,  H01L21/0214 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/823821 ,  H01L29/66795 ,  C23C14/228 ,  H01J37/32082 ,  H01J37/32174 ,  H01L21/76808 ,  H01L23/528

Abstract: A method of manufacturing a semiconductor device includes depositing a dielectric layer over a substrate, performing a first patterning to form an opening in the dielectric layer, and depositing an oxide film over and contacting the dielectric layer and within the opening in the dielectric layer. The oxide film is formed from multiple precursors that are free of O2, and depositing the oxide film includes forming a plasma of a first precursor of the multiple precursors.

公开(公告)号：US12027423B2

公开(公告)日：2024-07-02

申请号：US17813850

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Tai-Chun Huang ,  Jr-Hung Li ,  Tze-Liang Lee ,  Chi On Chui

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66545

Abstract: A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. The isolation regions extend into a semiconductor substrate. A portion of the semiconductor fin is etched to form a trench, which extends lower than bottom surfaces of the isolation regions, and extends into the semiconductor substrate. The method further includes filling the trench with a first dielectric material to form a first fin isolation region, recessing the first fin isolation region to form a first recess, and filling the first recess with a second dielectric material. The first dielectric material and the second dielectric material in combination form a second fin isolation region.

公开(公告)号：US12002675B2

公开(公告)日：2024-06-04

申请号：US17156365

申请日：2021-01-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yen-Yu Chen ,  Chih-Cheng Liu ,  Yi-Chen Kuo ,  Jr-Hung Li ,  Tze-Liang Lee ,  Ming-Hui Weng ,  Yahru Cheng

IPC: H01L21/027 ,  H01L21/308 ,  H01L21/311

CPC classification number: H01L21/0274 ,  H01L21/3086 ,  H01L21/31144

Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate and forming a dehydrated film over the photoresist layer. The photoresist layer is selectively exposed to actinic radiation to form an exposed portion and an unexposed portion of the photoresist layer. The photoresist layer is developed to remove the unexposed portion of the photoresist layer and a first portion of the dehydrated film over the unexposed portion of the photoresist layer. In an embodiment, the method includes etching the substrate by using the exposed portion of the photoresist layer as a mask.

公开(公告)号：US20240136184A1

公开(公告)日：2024-04-25

申请号：US18401800

申请日：2024-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Yu Chang ,  Jei Ming Chen ,  Tze-Liang Lee

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L21/0337 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76877

Abstract: A method of forming a semiconductor device includes forming a photoresist layer over a mask layer, patterning the photoresist layer, and forming an oxide layer on exposed surfaces of the patterned photoresist layer. The mask layer is patterned using the patterned photoresist layer as a mask. A target layer is patterned using the patterned mask layer a

公开(公告)号：US20240021476A1

公开(公告)日：2024-01-18

申请号：US18151181

申请日：2023-01-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Tze-Liang Lee ,  Jr-Hung Li ,  Chun-Kai Chen

IPC: H01L21/768 ,  H01L29/66

CPC classification number: H01L21/76897 ,  H01L29/6656 ,  H01L21/76813 ,  H01L29/66545

Abstract: In an embodiment, a device includes: a source/drain region over a semiconductor substrate; a dielectric layer over the source/drain region, the dielectric layer including a first dielectric material; an inter-layer dielectric over the dielectric layer, the inter-layer dielectric including a second dielectric material and an impurity, the second dielectric material different from the first dielectric material, a first portion of the inter-layer dielectric having a first concentration of the impurity, a second portion of the inter-layer dielectric having a second concentration of the impurity, the first concentration less than the second concentration; and a source/drain contact extending through the inter-layer dielectric and the dielectric layer to contact the source/drain region, the first portion of the inter-layer dielectric disposed between the source/drain contact and the second portion of the inter-layer dielectric.

公开(公告)号：US20230260832A1

公开(公告)日：2023-08-17

申请号：US17831884

申请日：2022-06-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Kai Lin ,  Po-Cheng Shih ,  Jr-Hung Li ,  Tze-Liang Lee

IPC: H01L21/768 ,  H01L23/535 ,  H01L23/532 ,  H01L21/02

CPC classification number: H01L21/76829 ,  H01L21/0228 ,  H01L21/02178 ,  H01L21/02205 ,  H01L21/76843 ,  H01L21/76895 ,  H01L23/535 ,  H01L23/53266

Abstract: Semiconductor devices and methods of manufacture are presented herein in which a etch stop layer is selectively deposited over a conductive contact. A dielectric layer is formed over the etch stop layer and an opening is formed through the dielectric layer and the etch stop layer to expose the conductive contact. Conductive material is then deposited to fill the opening.