公开(公告)号：US20080227283A1

公开(公告)日：2008-09-18

申请号：US12108001

申请日：2008-04-23

申请人： Cyril Cabral ,  Roy A. Carruthers ,  Christophe Detavernier ,  Simon Gaudet ,  Christian Lavoie ,  Huiling Shang

发明人： Cyril Cabral ,  Roy A. Carruthers ,  Christophe Detavernier ,  Simon Gaudet ,  Christian Lavoie ,  Huiling Shang

IPC分类号： H01L21/28

CPC分类号： H01L21/28525 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/665

摘要： A method for forming gennano-silicide contacts atop a Ge-containing layer that is more resistant to etching than are conventional silicide contacts that are formed from a pure metal is provided. The method of the present invention includes first providing a structure which comprises a plurality of gate regions located atop a Ge-containing substrate having source/drain regions therein. After this step of the present invention, a Si-containing metal layer is formed atop the said Ge-containing substrate. In areas that are exposed, the Ge-containing substrate is in contact with the Si-containing metal layer. Annealing is then performed to form a germano-silicide compound in the regions in which the Si-containing metal layer and the Ge-containing substrate are in contact; and thereafter, any unreacted Si-containing metal layer is removed from the structure using a selective etch process. In some embodiments, an additional annealing step can follow the removal step. The method of the present invention provides a structure having a germano-silicide contact layer atop a Ge-containing substrate, wherein the germano-silicide contact layer contains more Si than the underlying Ge-containing substrate.

摘要翻译： 提供了一种在与由纯金属形成的常规硅化物接触相比更耐蚀刻性的Ge含有层上方形成硅锗化物的方法。 本发明的方法包括首先提供一种结构，该结构包括位于其中具有源极/漏极区域的含Ge衬底顶部的多个栅极区域。 在本发明的该步骤之后，在所述含Ge基材上形成含Si金属层。 在暴露的区域中，含Ge衬底与含Si金属层接触。 然后进行退火以在含Si金属层和含Ge基板接触的区域中形成锗化硅化合物; 此后，使用选择性蚀刻工艺从结构中除去任何未反应的含Si金属层。 在一些实施方案中，附加的退火步骤可以跟随去除步骤。 本发明的方法提供了一种在含Ge衬底顶上具有锗硅化物接触层的结构，其中锗硅化物接触层含有比下面的含Ge衬底更多的Si。

公开(公告)号：US20080220581A1

公开(公告)日：2008-09-11

申请号：US12120286

申请日：2008-05-14

申请人： Scott D. Allen ,  Cyril Cabral ,  Kevin K. Dezfulian ,  Sunfei Fang ,  Brian J. Greene ,  Rajarao Jammy ,  Christian Lavoie ,  Zhijiong Luo ,  Hung Ng ,  Chun-Yung Sung ,  Clement H. Wann ,  Huilong Zhu

发明人： Scott D. Allen ,  Cyril Cabral ,  Kevin K. Dezfulian ,  Sunfei Fang ,  Brian J. Greene ,  Rajarao Jammy ,  Christian Lavoie ,  Zhijiong Luo ,  Hung Ng ,  Chun-Yung Sung ,  Clement H. Wann ,  Huilong Zhu

IPC分类号： H01L21/336

CPC分类号： H01L21/268 ,  H01L21/2686 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/28176 ,  H01L21/324 ,  H01L29/517 ,  H01L29/665

摘要： An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate.

摘要翻译： 用于形成场效应晶体管的光热退火方法使用反射金属栅极，使得当相邻的源极/漏极区域进行光热退火时，金属栅极的电特性以及金属栅极和栅极电介质之间的界面不受损害 金属门。 另一种光热退火方法可以用于同时光热退火：（1）硅层和形成硅化物的金属层以形成完全硅化的栅极; 和（2）源/漏区以形成退火的源/漏区。 附加的光热退火方法可以使用与热吸收层结合的热绝缘层来选择性地使硅层和形成硅化物的金属层光退火以形成完全硅化物栅极。

公开(公告)号：US20070034967A1

公开(公告)日：2007-02-15

申请号：US11537718

申请日：2006-10-02

申请人： Hasan Nayfeh ,  Mahender Kumar ,  Sunfei Fang ,  Jakub Kedzierski ,  Cyril Cabral

发明人： Hasan Nayfeh ,  Mahender Kumar ,  Sunfei Fang ,  Jakub Kedzierski ,  Cyril Cabral

IPC分类号： H01L29/94

CPC分类号： H01L21/823835 ,  H01L21/823842 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

摘要： A MOSFET structure and method of forming is described. The method includes forming a metal-containing layer that is thick enough to fully convert the semiconductor gate stack to a semiconductor metal alloy in a first MOSFET type region but only thick enough to partially convert the semiconductor gate stack to a semiconductor metal alloy in a second MOSFET type region. In one embodiment, the gate stack in a first MOSFET region is recessed prior to forming the metal-containing layer so that the height of the first MOSFET semiconductor stack is less than the height of the second MOSFET semiconductor stack. In another embodiment, the metal-containing layer is thinned over one MOSFET region relative to the other MOSFET region prior to the conversion process.

摘要翻译： 描述了MOSFET结构和形成方法。 该方法包括形成足够厚的含金属层，以将半导体栅极堆叠完全转换成第一MOSFET型区域中的半导体金属合金，但是仅仅足够厚以将第二半导体栅极堆叠部分地转换为半导体金属合金 MOSFET类型区域。 在一个实施例中，在形成含金属层之前，第一MOSFET区域中的栅极堆叠是凹进的，使得第一MOSFET半导体堆叠的高度小于第二MOSFET半导体堆叠的高度。 在另一个实施例中，在转换过程之前，含金属层相对于另一个MOSFET区域在一个MOSFET区域上变薄。

公开(公告)号：US20060124974A1

公开(公告)日：2006-06-15

申请号：US10905101

申请日：2004-12-15

申请人： Cyril Cabral ,  Bruce Doris ,  Thomas Kanarsky ,  Xiao Liu ,  Huilong Zhu

发明人： Cyril Cabral ,  Bruce Doris ,  Thomas Kanarsky ,  Xiao Liu ,  Huilong Zhu

IPC分类号： H01L29/80

CPC分类号： H01L29/7845 ,  H01L21/3215 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665

摘要： A semiconductor structure and method that is capable of generating a local mechanical gate stress for channel mobility modification are provided. The semiconductor structure includes at least one NFET and at least one PFET on a surface of a semiconductor substrate. The at least one NFET has a gate stack structure comprising a gate dielectric, a first gate electrode layer, a barrier layer, a Si-containing second gate electrode layer and a compressive metal, and the at least one PFET has a gate stack structure comprising a gate dielectric, a first gate electrode layer, a barrier layer and a tensile metal or a silicide.

摘要翻译： 提供了能够产生用于信道迁移率修改的局部机械栅极应力的半导体结构和方法。 半导体结构在半导体衬底的表面上包括至少一个NFET和至少一个PFET。 所述至少一个NFET具有包括栅极电介质，第一栅极电极层，阻挡层，含Si的第二栅极电极层和压缩金属的栅极堆叠结构，并且所述至少一个PFET具有包括 栅极电介质，第一栅电极层，阻挡层和拉伸金属或硅化物。

公开(公告)号：US20060121664A1

公开(公告)日：2006-06-08

申请号：US11254929

申请日：2005-10-20

申请人： Sunfei Fang ,  Cyril Cabral ,  Chester Dziobkowski ,  John Ellis-Monaghan ,  Christian Lavoie ,  Zhijiong Luo ,  James Nakos ,  An Steegen ,  Clement Wann

发明人： Sunfei Fang ,  Cyril Cabral ,  Chester Dziobkowski ,  John Ellis-Monaghan ,  Christian Lavoie ,  Zhijiong Luo ,  James Nakos ,  An Steegen ,  Clement Wann

IPC分类号： H01L21/8238 ,  H01L21/3205 ,  H01L21/44

CPC分类号： H01L21/28518 ,  H01L21/823814 ,  H01L21/823835

摘要： A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.

公开(公告)号：US20060001162A1

公开(公告)日：2006-01-05

申请号：US11084724

申请日：2005-03-18

申请人： Ronald Schutz ,  Werner Robl ,  Rajeev Malik ,  Lawrence Clevenger ,  Oleg Gluschenkov ,  Cyril Cabral ,  Roy Iggulden ,  Yun-Yu Wang ,  Keith Wong ,  Irene McStay

发明人： Ronald Schutz ,  Werner Robl ,  Rajeev Malik ,  Lawrence Clevenger ,  Oleg Gluschenkov ,  Cyril Cabral ,  Roy Iggulden ,  Yun-Yu Wang ,  Keith Wong ,  Irene McStay

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L21/7685 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/76838 ,  H01L21/76855 ,  H01L21/823828 ,  H01L21/823842 ,  H01L29/4941 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78 ,  H01L2221/1078

摘要： A conductive structure in an integrated circuit (12), and a method of forming the structure, is provided that includes a polysilicon layer (30), a thin layer containing titanium over the polysilicon, a tungsten nitride layer (34) over the titanium-containing layer and a tungsten layer over the tungsten nitride layer. The structure also includes a silicon nitride interfacial region (38) between the polysilicon layer and the titanium-containing layer. The structure withstands high-temperature processing without substantial formation of metal silicides in the polysilicon layer (30) and the tungsten layer (32), and provides low interface resistance between the tungsten layer and the polysilicon layer.

摘要翻译： 提供集成电路（12）中的导电结构和形成该结构的方法，其包括多晶硅层（30），在多晶硅上含有钛的薄层，在钛 - 钛层上的氮化钨层（34） 并且在氮化钨层上形成钨层。 该结构还包括在多晶硅层和含钛层之间的氮化硅界面区域（38）。 该结构经受高温处理，而在多晶硅层（30）和钨层（32）中基本不形成金属硅化物，并且在钨层和多晶硅层之间提供低的界面电阻。

公开(公告)号：US20050116230A1

公开(公告)日：2005-06-02

申请号：US10722557

申请日：2003-11-28

申请人： Cyril Cabral ,  Christophe Detavernier ,  Rajarao Jammy ,  Katherine Saenger

发明人： Cyril Cabral ,  Christophe Detavernier ,  Rajarao Jammy ,  Katherine Saenger

IPC分类号： H01L21/8238 ,  H01L27/108 ,  H01L29/49

CPC分类号： H01L29/4966 ,  H01L21/823842

摘要： A semiconductor device such as a complementary metal oxide semiconductor (CMOS) comprising at least one FET that comprises a gate electrode comprising a metal carbide and method of fabrication are provided. The CMOS comprises dual work function metal gate electrodes whereby the dual work functions are provided by a metal and a carbide of a metal.

摘要翻译： 提供了包括至少一个FET的半导体器件，例如互补金属氧化物半导体（CMOS），其包括包含金属碳化物的栅电极和制造方法。 CMOS包括双功能金属栅电极，由此双功能功能由金属和金属的碳化物提供。

公开(公告)号：US20050104216A1

公开(公告)日：2005-05-19

申请号：US10714966

申请日：2003-11-18

申请人： Cyril Cabral ,  Stefanie Chiras ,  Emanuel Cooper ,  Hariklia Deligianni ,  Andrew Kellock ,  Judith Rubino ,  Roger Tsai

发明人： Cyril Cabral ,  Stefanie Chiras ,  Emanuel Cooper ,  Hariklia Deligianni ,  Andrew Kellock ,  Judith Rubino ,  Roger Tsai

IPC分类号： B32B15/04 ,  C25D3/56 ,  C25D9/08 ,  H01L21/288 ,  H01L21/44 ,  H01L21/768 ,  H01L23/48 ,  H01L23/52 ,  H01L23/532 ,  H01L29/40

CPC分类号： H01L21/2885 ,  C25D9/08 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/53238 ,  H01L2224/05007

摘要： A composite material comprising a layer containing copper, and an electrodeposited CoWP film on the copper layer. The CoWP film contains from 11 atom percent to 25 atom percent phosphorus and has a thickness from 5 nm to 200 nm. The invention is also directed to a method of making an interconnect structure comprising: providing a trench or via within a dielectric material, and a conducting metal containing copper within the trench or the via; and forming a CoWP film by electrodeposition on the copper layer. The CoWP film contains from 10 atom percent to 25 atom percent phosphorus and has a thickness from 5 nm to 200 nm. The invention is also directed to a interconnect structure comprising a dielectric layer in contact with a metal layer; an electrodeposited CoWP film on the metal layer, and a copper layer on the CoWP film.

摘要翻译： 一种复合材料，其包含含有铜的层和在铜层上的电沉积CoWP膜。 CoWP膜含有11原子％至25原子％的磷并具有5nm至200nm的厚度。 本发明还涉及一种制造互连结构的方法，包括：在介电材料内提供沟槽或通孔，以及在沟槽或通孔内容纳铜的导电金属; 并通过电沉积在铜层上形成CoWP膜。 CoWP膜含有10原子％至25原子％的磷，并且具有5nm至200nm的厚度。 本发明还涉及包括与金属层接触的电介质层的互连结构; 金属层上的电沉积CoWP膜，CoWP膜上的铜层。

公开(公告)号：US20050087824A1

公开(公告)日：2005-04-28

申请号：US10605769

申请日：2003-10-24

申请人： Cyril Cabral ,  Omer Dokumaci ,  Oleg Gluschenkov

发明人： Cyril Cabral ,  Omer Dokumaci ,  Oleg Gluschenkov

IPC分类号： G05F1/10 ,  G05F3/02 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/51 ,  H01L29/76 ,  H01L29/772 ,  H01L29/78 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/28194 ,  H01L21/28202 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7836

摘要： field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETs. The FETs have a device channel and a gate above the device channel with a doped source/drain extension at said each end of the thin channel. A portion of a low resistance material layer (e.g., a silicide layer) is disposed on source/drain extensions. The portions on the doped extensions laterally form a direct contact with the doped source/drain extension. Any low resistance material layer on the gate is separated from the low resistance material portions on the source/drain extensions.

摘要翻译： 场效应晶体管（FET），包括FET的集成电路（IC）芯片和形成FET的方法。 FET在器件沟道上方具有器件沟道和栅极，在薄沟道的每个端部具有掺杂的源极/漏极延伸。 低电阻材料层（例如硅化物层）的一部分设置在源极/漏极延伸部分上。 掺杂延伸部分上的部分横向形成与掺杂源极/漏极延伸部的直接接触。 栅极上的任何低电阻材料层与源极/漏极延伸部分上的低电阻材料部分分离。

公开(公告)号：US20070229212A1

公开(公告)日：2007-10-04

申请号：US11758746

申请日：2007-06-06

申请人： Arne Ballantine ,  Cyril Cabral ,  Daniel Edelstein ,  Anthony Stamper

发明人： Arne Ballantine ,  Cyril Cabral ,  Daniel Edelstein ,  Anthony Stamper

IPC分类号： H01C10/00

CPC分类号： H01L28/20 ,  H01C7/006 ,  H01C17/242 ,  Y10T29/49082 ,  Y10T29/49099 ,  Y10T29/49105

摘要： An electrical structure. The electrical structure includes a resistor having a length L and an electrical resistance R(t) at a time t; and a laser radiation directed onto a portion of the resistor, wherein the portion of the resistor includes a fraction F of the length L, wherein the laser radiation heats the portion of the resistor such that the electrical resistance R(t) instantaneously changes at a rate dR/dt, and wherein the resistor is coupled to a semiconductor substrate.

摘要翻译： 电气结构。 电气结构包括在时间t具有长度L和电阻R（t）的电阻器; 以及引导到电阻器的一部分的激光辐射，其中电阻器的该部分包括长度为L的分数F，其中激光辐射加热电阻器的部分，使得电阻R（t）瞬时变化 速率dR / dt，并且其中所述电阻器耦合到半导体衬底。