公开(公告)号：US09553485B2

公开(公告)日：2017-01-24

申请号：US13436309

申请日：2012-03-30

Applicant: Manjit Singh ,  Siamak Bastami

Inventor： Manjit Singh ,  Siamak Bastami

IPC: H01F38/00 ,  H02J17/00 ,  H01F38/14 ,  H02J5/00

CPC classification number: H02J50/60 ,  G01V3/12 ,  H01F38/14 ,  H02J5/005 ,  H02J7/025 ,  H02J17/00 ,  H02J50/10 ,  H02J50/12 ,  H02J50/90 ,  Y02E60/12

Abstract: An inductive wireless power transfer system comprises a transmitter configured to generate an electromagnetic field to a coupling region for providing energy transfer to a wireless power receiving apparatus. The transmitter includes control logic configured to determine a power component of the transmitter, and determine a presence of a foreign object within the coupling region in response to a comparison of the power component and a desired threshold for the power component. Related inductive methods for detecting a foreign object in an inductive wireless power transfer coupling region of an inductive wireless power transfer system and operating a sleep mode of a wireless power transmitter are disclosed.

Abstract translation: 感应式无线电力传输系统包括被配置为向耦合区域产生电磁场以用于向无线电力接收装置提供能量传递的发射机。 所述发射机包括控制逻辑，所述控制逻辑被配置为响应于所述功率分量与所述功率分量的期望阈值的比较来确定所述发射机的功率分量，并且确定所述耦合区域内的异物的存在。 公开了一种用于检测感应无线电力传输系统的感应无线电力传输耦合区域中的异物并且操作无线电力发射器的睡眠模式的相关感应方法。

公开(公告)号：US09543960B1

公开(公告)日：2017-01-10

申请号：US14966913

申请日：2015-12-11

Applicant: Integrated Device Technology, Inc.

Inventor： Chengming He ,  Ruben Eribes ,  Denny Nathaniel Castile

IPC: H03K21/00 ,  H03K23/00 ,  H03K25/00 ,  H03K21/10 ,  H03K7/08

CPC classification number: H03K21/10 ,  H03K5/1565 ,  H03K7/08

Abstract: A multi-stage frequency divider includes a cascaded arrangement of first and second integer dividers configured to collectively divide a frequency of a periodic reference signal by an integer amount equal to a product of (2N+1) and (2M+1), where N and M are unequal positive integers greater than two. A duty cycle enhancement circuit is provided, which is synchronized to the periodic reference signal and configured to generate a periodic signal having 2MN+N+M cycles of high followed by 2MN+N+M+1 cycles of low or vice versa, where a duration of each cycle is equivalent to a period of the periodic reference signal. A duty cycle correction circuit is provided as a final stage and is configured to generate a periodic output signal having a uniform duty cycle from the periodic signal generated by the duty cycle enhancement circuit.

Abstract translation: 多级分频器包括第一和第二整数除法器的级联布置，其被配置为将周期性参考信号的频率共同等于（2N + 1）和（2M + 1）的乘积的整数，其中N 而M是不等于2的正整数。 提供了一种占空比增强电路，其与周期性参考信号同步，并被配置为产生具有2MN + N + M个高周期的周期信号，随后是低的2MN + N + M + 1个周期，反之亦然，其中a 每个周期的持续时间等于周期性参考信号的周期。 提供占空比校正电路作为最后级，并且被配置为从由占空比增强电路产生的周期信号产生具有均匀占空比的周期性输出信号。

公开(公告)号：US09506817B2

公开(公告)日：2016-11-29

申请号：US13470278

申请日：2012-05-12

Applicant: Feng Qiu

Inventor： Feng Qiu

IPC: G01K7/01

CPC classification number: G01K7/01

Abstract: Temperature accuracy is improved, conversion gain is increased without increasing current density and parasitic resistance errors and other problems with conventional bandgap reference temperature sensors are eliminated by generating a signal proportional to temperature from four samples, where the signal is defined as a difference between a first difference and a second difference, the first difference comprising a difference between the second sample and the first sample, the second difference comprising a difference between the fourth sample and the third sample, and where the signal is defined to cancel parasitic components in the first, second, third and fourth samples.

Abstract translation: 提高温度精度，增加转换增益而不增加电流密度和寄生电阻误差，并且通过产生与来自四个样本的温度成比例的信号来消除常规带隙参考温度传感器的其他问题，其中信号被定义为第一 差异和第二差异，所述第一差异包括所述第二样本和所述第一样本之间的差异，所述第二差异包括所述第四样本和所述第三样本之间的差异，并且其中所述信号被定义为抵消所述第一样本和所述第三样本之间的寄生分量， 第二，第三和第四个样本。

公开(公告)号：US09485688B1

公开(公告)日：2016-11-01

申请号：US14050210

申请日：2013-10-09

Applicant: Integrated Device Technology, Inc.

Inventor： Mohammad Shahanshah Akhter ,  Brian Scott Darnell ,  Steve Lamontagne ,  Bachir Berkane

IPC: H04W4/00 ,  H04W28/06

CPC classification number: H03M7/3091 ,  H03M7/6052 ,  H04L69/22

Abstract: The method and apparatus of the present invention provides for the compression and decompression of data bursts wherein the propagation of synchronization errors is limited to a desired number of signal samples and the start of a burst boundary is identified. In accordance with the present invention, a method and apparatus are provided for compressing data in a communication system by receiving data bursts comprising a plurality of uncompressed data packets at a compressor of the communication system, generating a start of burst parameter and a packet size parameter for each of the uncompressed data packets and compressing the data packets. At the decompressor, the compressed data packets are received and when a synchronization error occurs, the packet size parameter is used to limit the propagation of the error to a desired number of samples and to restore the data burst utilizing the start of burst parameter.

Abstract translation: 本发明的方法和装置提供数据脉冲串的压缩和解压缩，其中同步误差的传播被限制到期望数量的信号样本，并且识别出突发边界的开始。 根据本发明，提供一种方法和装置，用于在通信系统中通过在通信系统的压缩器处接收包括多个未压缩数据分组的数据突发来产生通信系统中的数据，产生突发参数开始和分组大小参数 对于每个未压缩的数据分组并压缩数据分组。 在解压缩器处，压缩的数据分组被接收，并且当发生同步错误时，分组大小参数被用于将误差的传播限制到期望数量的样本，并且使用突发参数的开始恢复数据突发。

公开(公告)号：US09479177B1

公开(公告)日：2016-10-25

申请号：US14575212

申请日：2014-12-18

Applicant: Integrated Device Technology, Inc.

Inventor： Brian Buell ,  Li Tao ,  Song Gao

IPC: H03K23/00 ,  H03K21/02 ,  H03L7/18 ,  H03L7/197 ,  H03L7/193 ,  H03K23/68

CPC classification number: H03L7/0992 ,  H03K21/02 ,  H03K23/68 ,  H03L7/0802 ,  H03L7/085 ,  H03L7/093 ,  H03L7/18 ,  H03L7/1806 ,  H03L7/193 ,  H03L7/1974 ,  H03L7/1976 ,  H03L2207/50

Abstract: A fractional divider (FD) includes a multi-modulus divider (MMD), which generates a periodic output signal in response to: (i) a periodic reference signal (REFHF), and (ii) a modulus control signal having a value that sets a frequency division ratio (1/P, 1/(P+1)) to be applied to the periodic reference signal. A phase correction circuit is provided, which generates an FD output signal in response to the periodic MMD output signal and a corrected multi-bit phase correction control (CPCC) signal during an active mode of operation. The phase correction circuit further generates an FD output signal in response to the periodic MMD output signal and a preliminary multi-bit phase correction control (PPCC) signal during a calibration mode of operation. A control circuit is provided, which generates the modulus control signal, the PPCC signal and the CPCC signal during the active mode of operation.

Abstract translation: 分数分频器（FD）包括多模式分频器（MMD），其响应于：（i）周期性参考信号（REFHF）产生周期性输出信号，以及（ii）具有设定值的模数控制信号 要施加到周期性参考信号的分频比（1 / P，1 /（P + 1））。 提供相位校正电路，其在活动操作模式期间响应于周期性MMD输出信号和校正的多位相位校正控制（CPCC）信号而产生FD输出信号。 相位校正电路还在校准操作模式期间响应周期性MMD输出信号和初步多位相位校正控制（PPCC）信号产生FD输出信号。 提供了一种控制电路，其在活动操作模式期间产生模数控制信号，PPCC信号和CPCC信号。

公开(公告)号：US09478599B1

公开(公告)日：2016-10-25

申请号：US14586525

申请日：2014-12-30

Applicant: Integrated Device Technology, Inc.

Inventor： Robert A. Gubser ,  Ajay Kumar Ghai ,  Viresh Piyush Patel

IPC: H01L23/495 ,  H01L23/02 ,  H01L23/04 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L49/02 ,  H01L23/50 ,  H01L23/552

CPC classification number: H01L28/10 ,  H01F27/00 ,  H01L21/50 ,  H01L23/10 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/50 ,  H01L23/552 ,  H01L23/645 ,  H01L2224/16225

Abstract: An integrated circuit device includes an integrated circuit substrate having an at least two piece package thereon. The package has a sealed cavity therein and a patterned metal inductor in the cavity. The inductor has at least a first terminal electrically coupled to a portion of the integrated circuit substrate by an electrically conductive via, which extends at least partially through the package. The package, which may include a material selected from a group consisting of glass and ceramics, includes a base and a cap sealed to the base. The metal inductor includes a metal layer patterned on at least one of the cap and base of the package. The base may also include first and second electrically conductive vias therein, which are electrically connected to first and second terminals of the inductor.

Abstract translation: 集成电路器件包括其上具有至少两个片的封装的集成电路衬底。 封装在其中具有密封腔，并且在空腔中具有图案化的金属电感器。 电感器具有至少第一端子，该第一端子通过导电通孔电连接到集成电路基板的一部分，导电通孔至少部分延伸穿过封装。 可以包括从由玻璃和陶瓷组成的组中选择的材料的包装包括基部和与基部密封的盖。 金属电感器包括在封装的帽和底座中的至少一个上图案化的金属层。 基座还可以包括其中的第一和第二导电通孔，其电连接到电感器的第一和第二端子。

公开(公告)号：US09455045B1

公开(公告)日：2016-09-27

申请号：US14691472

申请日：2015-04-20

Applicant: Integrated Device Technology, Inc.

Inventor： Xiaohong Zheng ,  Hui Li

IPC: G11C17/00 ,  G11C17/18 ,  G11C17/16

CPC classification number: G11C17/18 ,  G11C7/20 ,  G11C7/222 ,  G11C17/16

Abstract: The present invention provides a method and apparatus that includes a timing device circuit for generating a timing signal, a RAM coupled to the timing device circuit, an OTP NVM and selection logic. The RAM is operable upon receiving a burn address to read configuration data in the RAM beginning at the burn address and the OTP NVM is operable to burn the configuration data read from RAM into the OTP NVM. The OTP NVM is configured to read configuration data in the OTP NVM and the RAM is configured to store the configuration data from the OTP NVM beginning at an address in the RAM corresponding to a read start address to define a timing device configuration in the RAM.

Abstract translation: 本发明提供了一种方法和装置，其包括用于产生定时信号的定时装置电路，耦合到定时装置电路的RAM，OTP NVM和选择逻辑。 RAM可以在接收到刻录地址以从烧录地址开始读取RAM中的配置数据时操作，并且OTP NVM可操作地将从RAM读取的配置数据刻录到OTP NVM中。 OTP NVM被配置为读取OTP NVM中的配置数据，并且RAM被配置为从对应于读起始地址的RAM中的地址开始存储来自OTP NVM的配置数据，以定义RAM中的定时设备配置。

公开(公告)号：US09444566B1

公开(公告)日：2016-09-13

申请号：US14200619

申请日：2014-03-07

Applicant: Integrated Device Technology, Inc.

Inventor： Frederic Mustiere ,  Felix Duong ,  Alain Trottier ,  Russell Smiley ,  Peng Xiao

IPC: H04J3/06

CPC classification number: H04J3/0667 ,  H04L43/087 ,  H04L43/106

Abstract: Methods of performing time-of-day synchronization in a packet processing network include accumulating timestamps transmitted in packets between master and slave devices, which are synchronized to respective master and slave clocks and separated from each other by the packet processing network. Operations are also performed to determine whether first timestamps accumulated in a first direction across the packet network demonstrate that a first packet delay variation (PDV) sequence observed from the first timestamps is stationary. A phase offset between the master and slave clocks is then adjusted using a time-of-day (ToD) estimation algorithm. This adjusting can include evaluating a location-dependent statistic of the first PDV sequence.

Abstract translation: 在分组处理网络中执行时间同步的方法包括累积在主设备和从设备之间以分组发送的时间戳，其与相应的主时钟和从时钟同步并且由分组处理网络彼此分离。 还执行操作以确定跨分组网络在第一方向上累积的第一时间戳是否显示从第一时间戳观察到的第一分组延迟变化（PDV）序列是静止的。 然后使用时间（ToD）估计算法调整主时钟和从时钟之间的相位偏移。 该调整可以包括评估第一PDV序列的位置相关统计量。

公开(公告)号：US09431955B1

公开(公告)日：2016-08-30

申请号：US14985689

申请日：2015-12-31

Applicant: Integrated Device Technology, Inc.

Inventor： James Bryan Northcutt ,  Eugene Stanley Trefethen ,  Harry LeRoy Sutter ,  Stephen Amar Tibbitts ,  Charles Michael Rice ,  Bruce Edward Clark

IPC: H03B5/04 ,  H03B5/32 ,  H03H9/10 ,  H03H9/13 ,  H03H9/205

CPC classification number: G01R31/2884 ,  G01R31/282 ,  G01R31/2836 ,  G01R31/2853 ,  H03B5/04 ,  H03B5/32 ,  H03B5/36 ,  H03H9/02133 ,  H03H9/02834 ,  H03H9/02897 ,  H03H9/0547 ,  H03H9/10 ,  H03H9/1021 ,  H03H9/13 ,  H03H9/205 ,  H03H11/44

Abstract: An integrated circuit device includes a pair of serially-connected crystal resonators arranged as a first crystal resonator, which is configured to preferentially support a fundamental resonance mode in response to an input signal, and a second crystal resonator, which is configured to preferentially support a third or higher overtone resonance mode in response to a signal generated at an output terminal of the first crystal resonator. A negative impedance converter (NIC) is also provided, which has an input terminal electrically connected to an input terminal of the first crystal resonator and an output terminal electrically connected to one of the output terminal of the first crystal resonator and the output terminal of the second crystal resonator. The NIC may be a CMOS-based NIC that is devoid of inductive reactance from a passive inductor.

Abstract translation: 集成电路器件包括一对串联连接的晶体谐振器，被布置为第一晶体谐振器，其被配置为优先支持响应于输入信号的基本谐振模式;以及第二晶体谐振器，其被配置为优先支持 响应于在第一晶体谐振器的输出端产生的信号而产生第三或更高泛音谐振模式。 还提供了一种负阻抗转换器（NIC），其具有电连接到第一晶体谐振器的输入端子的输入端子和电连接到第一晶体谐振器的输出端子和输出端子的输出端子 第二个晶体谐振器。 NIC可能是基于CMOS的NIC，没有来自无源电感的感抗。

公开(公告)号：US09419588B1

公开(公告)日：2016-08-16

申请号：US14628215

申请日：2015-02-21

Applicant: Integrated Device Technology, Inc.

Inventor： John Hsu

IPC: H03K3/01 ,  H03K3/012

CPC classification number: H04L25/0278 ,  H03K3/012 ,  H03K19/0005 ,  H03K19/00384 ,  H03K19/018571

Abstract: An output driver is provided that adapts an output impedance of the output driver to the voltage level of a power supply, thereby providing a constant output impedance over a range of different operating voltages. The output driver includes a plurality of individual driver circuits, each one of the plurality of individual driver circuits configured to provide a plurality of predetermined output impedances in response to a plurality of power supply voltage level inputs and a decoder. The decoder of the output driver is configured for receiving a digital codeword representative of a voltage level of a power supply coupled to the output driver and for decoding the digital codeword to activate one or more of the individual driver circuits to provide a constant output impedance from the output driver in response to the voltage level of the power supply coupled to the output driver, wherein the constant output impedance is a combination of the predetermined output impedances of the activated individual driver circuits.

Abstract translation: 提供了一种输出驱动器，其将输出驱动器的输出阻抗调整到电源的电压电平，从而在不同工作电压范围内提供恒定的输出阻抗。 输出驱动器包括多个单独的驱动器电路，多个单独驱动器电路中的每一个被配置为响应于多个电源电压电平输入和解码器而提供多个预定的输出阻抗。 输出驱动器的解码器被配置为用于接收代表耦合到输出驱动器的电源的电压电平的数字代码字，并且用于对数字代码字进行解码以激活单个驱动器电路中的一个或多个以提供恒定的输出阻抗 所述输出驱动器响应于耦合到所述输出驱动器的电源的电压电平，其中所述恒定输出阻抗是所激活的各个驱动器电路的预定输出阻抗的组合。