Abstract:
Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.
Abstract:
There is provided a method and apparatus of expanding capacity for a cache array. The method includes in response to detecting that a first new cache disk is to be added to a first cache array, initializing the first new cache disk without disabling other cache disks in the first cache array; allocating a storage space for a cache page metadata based on a result of the initializing; storing the cache page metadata into an initialized directory logical unit number, DIR LUN; storing a copy of the cache page metadata from a memory into the DIR LUN to facilitate the first cache disk to be in a ready state; and in response to the first new cache disk being in the ready state, configuring the first new cache disk as being in an initialized state to expand the capacity of the first cache array.
Abstract:
A dual-mode, dual-display shared resource computing (SRC) device is usable to stream SRC content from a host SRC device while in an on-line mode and maintain functionality with the content during an off-line mode. Such remote SRC devices can be used to maintain multiple user-specific caches and to back-up cached content for multi-device systems.
Abstract:
Provided is a memory mapping method, and particularly provided is a nonvolatile main memory mapping method for managing a nonvolatile main memory. The nonvolatile memory mapping method includes: performing a system call in order to access a file page that is required to operate a process stored in a kernel area of a nonvolatile main memory, wherein both the file page and process are stored in the kernel area of the nonvolatile main memory; and mapping a physical address of the file page to a virtual address of a user area of the nonvolatile main memory.
Abstract:
The storage processor of a data storage system such as a storage array automatically uses a first portion of an accelerator cache storage device for an accelerator cache and a second portion of the accelerator cache storage device for a physical storage tier upon detecting the presence of the accelerator cache storage device installed in the data storage system, such as when a storage device is plugged into a designated slot of the data storage system, without requiring any user configuration of the accelerator cache or physical storage tier and without specification by the user of the type(s) of data to be cached in the accelerator cache or stored in the physical storage tier.
Abstract:
A hybrid hard disk drive (HDD) that includes a magnetic storage medium and a nonvolatile solid-state device limits the amount of data that are stored in the solid-state storage device but are not also stored in the magnetic storage device. By limiting such “flash-only” data to as much as can be flushed to the magnetic storage medium within a specified time, the hybrid HDD can flush all flash-only data to the magnetic storage medium immediately prior to a power-off of the drive. Thus, the hybrid HDD can employ a write cache, which relies on storing flash-only data in the hybrid HDD, without the disadvantage of storing flash-only data after shut-down.
Abstract:
A hybrid hard disk drive (HDD) that includes a magnetic storage medium and a nonvolatile solid-state device limits the amount of data that are stored in the solid-state storage device but are not also stored in the magnetic storage device. By limiting such “flash-only” data to as much as can be flushed to the magnetic storage medium within a specified time, the hybrid HDD can flush all flash-only data to the magnetic storage medium immediately prior to a power-off of the drive. Thus, the hybrid HDD can employ a write cache, which relies on storing flash-only data in the hybrid HDD, without the disadvantage of storing flash-only data after shut-down.
Abstract:
Systems and methods for performing adaptive host memory buffer caching of transition layer tables (FTL tables) are disclosed. In one form a non-volatile memory system receives, in conjunction with receiving a first host command from a host system, hint information from the host system identifying a file stored at the non-volatile memory system that the host system will read data from. The non-volatile memory system identifies one or more FTL tables that are associated with data of the file identified in the hint information and sends the one or more FTL tables to the host system for storage in a host memory buffer at the host system. After sending the one or more FTL tables to the host system, the non-volatile memory system receives a second host command from the host system, the host command including an instruction to read data from one or more physical block addresses at the non-volatile memory system storing data of the file.
Abstract:
A disclosed example apparatus includes a row address register (412) to store a row address corresponding to a row (608) in a memory array (602). The example apparatus also includes a row decoder (604) coupled to the row address register to assert a signal on a wordline (704) of the row after the memory receives a column address. In addition the example apparatus includes a column decoder (606) to selectively activate a portion of the raw based on the column address and the signal asserted on the wordline.
Abstract:
A computational device maintains a first type of cache and a second type of cache. The computational device receives a command from the host to release space. The computational device synchronously discards tracks from the first type of cache, and asynchronously discards tracks from the second type of cache.