公开(公告)号：US20240206169A1

公开(公告)日：2024-06-20

申请号：US18351992

申请日：2023-07-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masaaki HIGASHITANI ,  Peter RABKIN ,  Hiroyuki KINOSHITA

IPC: H10B43/27 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H10B43/30

CPC classification number: H10B43/27 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H10B43/30

Abstract: A semiconductor structure includes a vertical stack of repetition units, where each instance of the repetition unit extends along a first horizontal direction and includes a first electrically conductive strip, a first memory film located over the first electrically conductive strip, discrete semiconductor channels that are laterally spaced apart from each other along the first horizontal direction and located above the first memory film, a second memory film located above the discrete semiconductor channels, a second electrically conductive strip located above the second memory film, and an insulating strip located above the first electrically conductive strip. Source/drain openings are arranged along the first horizontal direction, interlaced with the discrete semiconductor channels, and vertically extending through the vertical stack of repetition units, and source/drain pillar structures are located in respective source/drain openings, and vertically extending through the vertical stack of repetition units.

公开(公告)号：US20240203512A1

公开(公告)日：2024-06-20

申请号：US18355343

申请日：2023-07-19

Applicant: SanDisk Technologies LLC

Inventor： Longju Liu ,  Sarath Puthenthermadam ,  Jiahui Yuan

IPC: G11C16/34 ,  G11C16/10

CPC classification number: G11C16/3459 ,  G11C16/10

Abstract: An apparatus is provided that includes a control circuit coupled to a plurality of non-volatile memory cells. The control circuit is configured to perform a program-verify iteration on a first set of the non-volatile memory cells in a plurality of program loops, determine that the first set of the non-volatile memory cells passes verification to a particular programmed state in a first number of program loops, determine a first voltage based on the first number of program loops, add an adaptive voltage offset to the first voltage to obtain a second voltage, and program a second set of the non-volatile memory cells in a plurality of program loops using the second voltage. The adaptive voltage offset varies as a function of temperature.

公开(公告)号：US20240203500A1

公开(公告)日：2024-06-20

申请号：US18337275

申请日：2023-06-19

Applicant: SK hynix Inc.

Inventor： Jae Yeop JUNG ,  Dong Hun KWAK ,  Chan Hui JEONG

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/3459

Abstract: A memory device includes: memory cells connected between a common source line and bit lines; a source line driver for applying a common source line voltage to the common source line and then floating the common source line; and a program operation controller for controlling the source line driver to change a length of a floating period in which the common source line is floated, based on a degree to which a program operation on the memory cells is performed.

公开(公告)号：US20240194243A1

公开(公告)日：2024-06-13

申请号：US18581018

申请日：2024-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hee-Woong KANG ,  Dong-Hun KWAK ,  Jun-Ho SEO ,  Hee-Won LEE

IPC: G11C11/4074 ,  G11C7/10 ,  G11C7/12 ,  G11C8/12 ,  G11C11/408 ,  G11C11/4097 ,  G11C11/56 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30 ,  G11C16/34

CPC classification number: G11C11/4074 ,  G11C7/109 ,  G11C7/12 ,  G11C8/12 ,  G11C11/4082 ,  G11C11/4085 ,  G11C11/4097 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30 ,  G11C16/3436 ,  G11C2207/2209

Abstract: A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.

公开(公告)号：US12008268B2

公开(公告)日：2024-06-11

申请号：US17867008

申请日：2022-07-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daehoon Na ,  Jeongdon Ihm ,  Jangwoo Lee ,  Byunghoon Jeong

IPC: G06F3/06 ,  G06F1/06 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/04

CPC classification number: G06F3/0659 ,  G06F1/06 ,  G06F3/0611 ,  G06F3/0656 ,  G06F3/0679 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/0483

Abstract: A memory system includes a memory device including a plurality of non-volatile memories and an interface circuit connected to each of the plurality of non-volatile memories, and a memory controller connected to the interface circuit and configured to transmit/receive data according to a first clock, wherein the interface circuit is configured to divide the first clock into a second clock, according to the number of the plurality of non-volatile memories, and transmit/receive data to/from each of the plurality of non-volatile memories, according to the second clock.

公开(公告)号：US12002517B2

公开(公告)日：2024-06-04

申请号：US17534210

申请日：2021-11-23

Applicant: SK hynix Inc.

Inventor： Hee Youl Lee

IPC: G11C16/24 ,  G11C16/10 ,  G11C16/14

CPC classification number: G11C16/24 ,  G11C16/10 ,  G11C16/14

Abstract: A semiconductor memory device includes a memory cell array, a page buffer, and control logic. The memory cell array includes a plurality of memory cells for storing data. The page buffer is coupled to at least one memory cell among the plurality of memory cells through a bit line and is configured to store data in the at least one memory cell. The control logic is configured to control an operation of the page buffer. The page buffer includes a first transistor coupled between the bit line and a first node, a second transistor coupled between the bit line and an external power voltage terminal, and an internal operation circuit coupled to the first node.

公开(公告)号：US12002514B2

公开(公告)日：2024-06-04

申请号：US17706097

申请日：2022-03-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Won Park ,  Won-Taeck Jung ,  Han-Jun Lee ,  Su Chang Jeon

IPC: G11C8/12 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/3459 ,  G11C8/12

Abstract: A nonvolatile memory may include; a first memory cell array including a first selection transistor connected to a first string selection line, a second memory cell array including a second selection transistor connected to a second string selection line and spaced apart from the first string selection line by a first cutting line, and a peripheral circuit. The peripheral circuit may provide a first program voltage to the first selection transistor, provide a second program voltage to the second selection transistor different from the first program voltage, program the first selection transistor with a first threshold voltage in response to the first program voltage, and program the second selection transistor with a second threshold voltage level greater than the first threshold voltage in response to the second program voltage.

公开(公告)号：US12001336B2

公开(公告)日：2024-06-04

申请号：US17585165

申请日：2022-01-26

Applicant: Micron Technology, Inc.

Inventor： Umberto Siciliani ,  Violante Moschiano ,  Walter Di Francesco

IPC: G06F12/0842 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/30 ,  G11C16/34

CPC classification number: G06F12/0842 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/30 ,  G11C16/3459 ,  G06F2212/1024

Abstract: A memory device includes a page buffer with a cache register and data registers, a memory array with a set of sub-blocks of memory cells configured as single-level cell (SLC) memory, and control logic. The control logic performs operations including: causing a first page of SLC data to be stored in the cache register; causing the first page of the SLC data to be moved from the cache register to a first data register; causing a subsequent page of the SLC data to be stored in the cache register; causing the SLC data stored in the cache register and in the data registers to be concurrently programmed to the set of sub-blocks, where the first page is programmed to a first sub-block and the subsequent page is programmed to a subsequent sub-block; and causing a subset of the operations for programming the set of sub-blocks to be performed in parallel.

公开(公告)号：US20240177773A1

公开(公告)日：2024-05-30

申请号：US18295726

申请日：2023-04-04

Applicant: SK hynix Inc.

Inventor： Hyung Jin CHOI ,  Gwi Han KO

IPC: G11C16/10 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C16/3459

Abstract: A memory device comprising: a memory cell array comprising multiple memory cells, and a controller configured to repeatedly perform a program loop comprising a voltage application interval and a verification interval until a program operation for cells that have been connected to a word line that have been selected as a program target reach a threshold voltage level and configured to adjust an increase in a level of a program voltage that is applied to the selected word line in the voltage application interval of a second program loop following a first program loop, based on a result of a comparison between a threshold voltage level of each of cells that have been selected as a verification target, among the cells that have been connected to the selected word line, and a pre-target level in the verification interval of the first program loop, among the program loops that are repeated.

公开(公告)号：US11996152B2

公开(公告)日：2024-05-28

申请号：US17481020

申请日：2021-09-21

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Kun Zhang ,  Yuancheng Yang ,  Wenxi Zhou ,  Wei Liu ,  Zhiliang Xia ,  Liang Chen ,  Yanhong Wang

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  H01L23/522 ,  H01L23/528 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a first bonding interface between the first semiconductor structure and the second semiconductor structure, and a second bonding interface between the first semiconductor structure and the third semiconductor structure. The first semiconductor structure includes an array of NAND memory strings and a first semiconductor layer in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a first peripheral circuit of the array of NAND memory strings including a first transistor, and a second semiconductor layer in contact with the first transistor. A third semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a third semiconductor layer in contact with the second transistor. The second semiconductor layer is between the first bonding interface and the first peripheral circuit. The second peripheral circuit is between the second bonding interface and the third semiconductor layer.