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    Semiconductor device and related fabrication methods
    41.
    发明授权
    Semiconductor device and related fabrication methods 有权
    半导体器件及相关制造方法

    公开(公告)号：US08748981B2

    公开(公告)日：2014-06-10

    申请号：US13606438

    申请日：2012-09-07

    Applicant: Hongning Yang ,  Xin Lin ,  Jiang-Kai Zuo

    Inventor： Hongning Yang ,  Xin Lin ,  Jiang-Kai Zuo

    IPC: H01L29/66 ,  H01L29/76

    CPC classification number: H01L29/66719 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1087 ,  H01L29/402 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/7809 ,  H01L29/7812

    Abstract: Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a first vertical drift region of semiconductor material, a second vertical drift region of semiconductor material, and a buried lateral drift region of semiconductor material that abuts the vertical drift regions. In one or more embodiments, the vertical drift regions and buried lateral drift region have the same conductivity type, wherein a body region of the opposite conductivity type overlies the buried lateral drift region between the vertical drift regions.

    Abstract translation: 提供半导体器件结构和相关的制造方法。 示例性的半导体器件结构包括半导体材料的第一垂直漂移区域，半导体材料的第二垂直漂移区域和邻接垂直漂移区域的半导体材料的埋入横向漂移区域。 在一个或多个实施例中，垂直漂移区域和掩埋横向漂移区域具有相同的导电类型，其中相反导电类型的体区域覆盖在垂直漂移区域之间的掩埋横向漂移区域。

    Method for manufacturing semiconductor substrate, and semiconductor device
    42.
    发明授权
    Method for manufacturing semiconductor substrate, and semiconductor device 有权
    半导体基板的制造方法以及半导体装置

    公开(公告)号：US08653536B2

    公开(公告)日：2014-02-18

    申请号：US13965275

    申请日：2013-08-13

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shunpei Yamazaki

    IPC: H01L29/15

    CPC classification number: H01L29/1608 ,  H01L21/76254 ,  H01L21/8213 ,  H01L21/84 ,  H01L27/12 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/7394 ,  H01L29/7812 ,  H01L29/7824 ,  H01L29/7833

    Abstract: An object is to provide a novel manufacturing method of a semiconductor substrate containing silicon carbide, and another object is to provide a semiconductor device using silicon carbide. A semiconductor substrate is manufactured through the steps of: adding ions to a silicon carbide substrate to form an embrittlement region in the silicon carbide substrate; bonding the silicon carbide substrate to a base substrate with insulating layers interposed therebetween; heating the silicon carbide substrate and separating the silicon carbide substrate at the embrittlement region to form a silicon carbide layer over the base substrate with the insulating layers interposed between therebetween; and performing heat treatment on the silicon carbide layer at a temperature of 1000° C. to 1300° C. to reduce defects of the silicon carbide layer. A semiconductor device is manufactured using the semiconductor substrate formed as described above.

    Abstract translation: 本发明的目的是提供一种含有碳化硅的半导体衬底的新颖制造方法，另一个目的是提供一种使用碳化硅的半导体器件。 通过以下步骤制造半导体衬底：向碳化硅衬底添加离子以在碳化硅衬底中形成脆化区; 将所述碳化硅衬底粘合到具有插入其间的绝缘层的基底衬底; 加热碳化硅衬底并在脆化区域分离碳化硅衬底以在基底衬底上形成碳化硅层，其间插入有绝缘层; 并在1000℃至1300℃的温度下对碳化硅层进行热处理以减少碳化硅层的缺陷。 使用如上所述形成的半导体衬底制造半导体器件。

    SOI LATERAL MOSFET DEVICES
    44.
    发明申请
    SOI LATERAL MOSFET DEVICES 有权
    SOI侧向MOSFET器件

    公开(公告)号：US20130193509A1

    公开(公告)日：2013-08-01

    申请号：US13131779

    申请日：2010-08-10

    Applicant: Xiaorong Luo ,  Florin Udrea

    Inventor： Xiaorong Luo ,  Florin Udrea

    IPC: H01L29/78

    CPC classification number: H01L29/7813 ,  H01L27/1203 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7809 ,  H01L29/7812

    Abstract: The present invention relates to a semiconductor power device and power integrated circuits (ICs). The lateral SOI MOSFET in the present comprises a trench gate extended to the dielectric buried layer, one or multiple dielectric trenches in the drift region, and a buried gate in said dielectric trench. The permittivity of the dielectric in said dielectric trench is lower than that of said active layer. Firstly, said dielectric trench not only greatly improves breakdown voltage, but also reduces pitch size. Secondly, the trench gate widens the effective conductive region in the vertical direction. Thirdly, dual gates of said trench gate and buried gate increase channel and current densities. Thereby, specific on-resistance and the power loss are reduced. The device of the present invention has many advantages, such as high voltage, high speed, low power loss, low cost and ease of integration. The device in the present invention is particularly suitable for power integrated circuits and RF power integrated circuits.

    Abstract translation: 本发明涉及半导体功率器件和功率集成电路（IC）。 本发明的横向SOI MOSFET包括延伸到电介质掩埋层的沟槽栅极，漂移区域中的一个或多个电介质沟槽以及所述电介质沟槽中的掩埋栅极。 电介质在所述电介质沟槽中的介电常数低于所述有源层的介电常数。 首先，所述电介质沟槽不仅大大提高了击穿电压，还降低了间距尺寸。 其次，沟槽栅极使垂直方向上的有效导电区域变宽。 第三，所述沟槽栅极和掩埋栅极的双栅极增加了沟道和电流密度。 从而，降低了特定导通电阻和功率损耗。 本发明的器件具有高电压，高速，低功耗，低成本，易集成等诸多优点。 本发明的器件特别适用于功率集成电路和RF功率集成电路。

    Method for Forming a Semiconductor Device
    46.
    发明申请
    Method for Forming a Semiconductor Device 有权
    形成半导体器件的方法

    公开(公告)号：US20120289003A1

    公开(公告)日：2012-11-15

    申请号：US13547339

    申请日：2012-07-12

    Applicant: Franz Hirler ,  Andreas Meiser

    Inventor： Franz Hirler ,  Andreas Meiser

    IPC: H01L21/336 ,  H01L21/331

    CPC classification number: H01L29/732 ,  H01L21/76224 ,  H01L21/76898 ,  H01L23/481 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/42304 ,  H01L29/42372 ,  H01L29/66272 ,  H01L29/66295 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7812 ,  H01L29/7813 ,  H01L29/7815 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method for forming a semiconductor device is provided. The method includes providing a wafer-stack having a main horizontal surface, an opposite surface, a buried dielectric layer, a semiconductor wafer extending from the buried dielectric layer to the main horizontal surface, and a handling wafer extending from the buried dielectric layer to the opposite surface; etching a deep vertical trench into the semiconductor wafer at least up to the buried dielectric layer, wherein the buried dielectric layer is used as an etch stop; forming a vertical transistor structure comprising forming a first doped region in the semiconductor wafer; forming a first metallization on the main horizontal surface in ohmic contact with the first doped region; removing the handling wafer to expose the buried dielectric layer; and masked etching of the buried dielectric layer to partly expose the semiconductor wafer on a back surface opposite to the main horizontal surface.

    Abstract translation: 提供一种形成半导体器件的方法。 该方法包括提供具有主水平表面，相对表面，埋入介质层，从掩埋介电层延伸到主水平表面的半导体晶片的晶片堆叠，以及从掩埋介电层延伸到 对面 将深的垂直沟槽蚀刻到至少直到埋入的介电层的半导体晶片内，其中埋入的介电层用作蚀刻停止层; 形成垂直晶体管结构，包括在半导体晶片中形成第一掺杂区; 在所述主水平表面上与所述第一掺杂区域欧姆接触形成第一金属化; 去除所述处理晶片以暴露所述埋入的介电层; 以及掩埋的介电层的掩模蚀刻以在与主水平表面相对的背面部分地暴露半导体晶片。

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