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    Analog to digital converter
    41.
    发明授权
    Analog to digital converter 失效
    模数转换器

    公开(公告)号：US4939518A

    公开(公告)日：1990-07-03

    申请号：US248374

    申请日：1988-09-23

    Applicant: Masao Hotta ,  Toshihiko Shimizu ,  Kenzi Maio ,  Yoshito Nejime

    Inventor： Masao Hotta ,  Toshihiko Shimizu ,  Kenzi Maio ,  Yoshito Nejime

    IPC: H03M1/12 ,  H03M1/20 ,  H03M1/36

    CPC classification number: H03M1/206 ,  H03M1/1235 ,  H03M1/365

    Abstract: In a cyclic averaging analog to digital converter, reference voltages having a plurality of levels, each of which is inputted to one of a plurality of comparators in a flash type analog to digital converter, are shifted cyclically by a small voltage, and the outputs of the flash type analog to digital converter are added for every shift cycle in order to obtain an output digital signal. The outputs of a voltage dividing circuit provide the reference voltages with N levels, the levels differing cyclically by a small voltage. The N reference voltages are divided into groups, each of which consists of M elements N/M, switches are provided each of which selects one of the reference voltages one after another for an associated group N/M reference voltages are thus selected by these switches and are supplied to the comparators.

    Abstract translation: 在循环平均模数转换器中，具有多个电平的参考电压，每个电平被输入到闪存类型模数转换器中的多个比较器中的一个，周期性地被小电压移位，并且输出 为每个移位周期添加闪存型模数转换器，以获得输出数字信号。 分压电路的输出为N个电平提供参考电压，该电平周期性地受到小电压的限制。 N个参考电压被分成组，每个组由M个元件N / M组成，提供开关，每个选择一个参考电压一个接一个地为相关联的组N / M参考电压由这些开关选择 并提供给比较器。

    Parallel analog-to-digital converter using 2.sup.(n-1) comparators
    42.
    发明授权
    Parallel analog-to-digital converter using 2.sup.(n-1) comparators 失效
    使用2（n-1）比较器的并行模数转换器

    公开(公告)号：US4928103A

    公开(公告)日：1990-05-22

    申请号：US408278

    申请日：1989-09-18

    Applicant: Charles D. Lane

    Inventor： Charles D. Lane

    IPC: H03M1/20 ,  H03M1/36

    CPC classification number: H03M1/206 ,  H03M1/361

    Abstract: The invention comprises an n-bit analog-to-digital flash converter comprising 2.sup.n /2 input comparators, each having a first input coupled to receive the analog voltage to be converted and a second input coupled to a different reference voltage. The reference voltages of each consecutive input comparator are spaced apart two LSBs of the converter. Each input comparator has two output, OUT and an inverted version thereof, OUT. 2.sup.n -1 consecutive latches are provided. Every other latch receives at its inputs the OUT and OUT signals from a single associated input comparator. All other latches receive the OUT signal of one of the input comparators and the OUT signal of an adjacent input comparator. The latches having inputs coupled to the OUT and OUT signals of a single input comparator produce a comparison output which change state every two LSBs of the converter and the latches having one input coupled to the OUT signal of one input comparator and the OUT signal of an adjacent input comparator produce comparison signals which change state halfway between the output signals of the adjacent latches. Thus, a comparison output is provided for every LSB of the full scale range of the converter using only 2.sup.n /2 input comparators.

    Abstract translation: 本发明包括一个包括2n / 2个输入比较器的n位模数转换闪存转换器，每个具有耦合以接收要转换的模拟电压的第一输入和耦合到不同参考电压的第二输入。 每个连续输入比较器的参考电压间隔开转换器的两个LSB。 每个输入比较器有两个输出OUT和它们的反向版本，并且提供了2n-1个连续的锁存器。 每个其他锁存器在其输入端接收来自单个相关输入比较器的OUT和＆amp; upbar＆O信号。 所有其他锁存器都接收输入比较器之一的OUT信号和相邻输入比较器的＆upbar＆O信号。 具有耦合到单个输入比较器的OUT和＆amp; upbar＆O信号的输入的锁存器产生比较输出，其改变转换器的每两个LSB的状态，并且具有耦合到一个输入比较器的OUT信号的一个输入的锁存器和＆amp; 相邻输入比较器产生比较信号，其改变相邻锁存器的输出信号之间的状态。 因此，仅使用2n / 2输入比较器，为转换器满量程范围的每个LSB提供比较输出。

    SAR ANALOG-TO-DIGITAL CONVERSION METHOD AND SAR ANALOG-TO-DIGITAL CONVERSION CIRCUIT
    43.
    发明申请
    SAR ANALOG-TO-DIGITAL CONVERSION METHOD AND SAR ANALOG-TO-DIGITAL CONVERSION CIRCUIT 有权
    SAR模拟到数字转换方法和SAR模拟数字转换电路

    公开(公告)号：US20140354458A1

    公开(公告)日：2014-12-04

    申请号：US14249973

    申请日：2014-04-10

    Applicant: FUJITSU SEMICONDUCTOR LIMITED

    Inventor： Tomoya KAKAMU

    IPC: H03M1/12 ,  H03M1/46

    CPC classification number: H03M1/38 ,  H03M1/129 ,  H03M1/162 ,  H03M1/206 ,  H03M1/44 ,  H03M1/468

    Abstract: An SAR analog-to-digital conversion circuit includes: first and second CDACs; first to third comparators respectively comparing outputs of the first and second CDACs, output levels of the first and third CDACs with a reference level; an arithmetic operation circuit; and an SAR control circuit, wherein the SAR control circuit: at each step, determines in which of four ranges output levels of the sampled and held signals of the first and second CDACs are included, the four ranges corresponding to the conversion range being quartered, determines two bits of the digital data and adjusts the output levels of the first and second CDACs so that a level at 1/4 or 3/4 of the voltage range agrees with the intermediate level, and controls first and second switches so that the voltage range is set to be a conversion range at a next step.

    Abstract translation: SAR模数转换电路包括：第一和第二CDAC; 分别比较第一和第二CDAC的输出，第一和第三CDAC的输出电平与参考电平的第一至第三比较器; 算术运算电路; SAR控制电路，其中所述SAR控制电路：在每个步骤中确定在四个范围中的哪一个范围中包括所述第一和第二CDAC的采样和保持的信号的输出电平，所述四个范围对应于转换范围， 确定数字数据的两位，并调整第一和第二CDAC的输出电平，使得电压范围的1/4或3/4电平与中间电平一致，并且控制第一和第二开关，使得电压 范围设定为下一步的转换范围。

    Time interpolation flash ADC having automatic feedback calibration
    44.
    发明授权
    Time interpolation flash ADC having automatic feedback calibration 有权
    具有自动反馈校准的时间插值闪光ADC

    公开(公告)号：US07737875B2

    公开(公告)日：2010-06-15

    申请号：US12270609

    申请日：2008-11-13

    Applicant: Mikko Waltari ,  Costantino Pala

    Inventor： Mikko Waltari ,  Costantino Pala

    IPC: H03M1/34 ,  H03M1/50

    CPC classification number: H03M1/206 ,  H03M1/1061 ,  H03M1/362 ,  H03M1/365 ,  H03M1/50

    Abstract: An input signal is compared to 2N−1 reference voltages to generate 2N−1 corresponding binary valued comparison signals, delaying at least one of the comparison signals by a variable delay and detecting a difference in arrival time between the delayed signal and another comparison signal. A time interpolation signal encoding a plurality of bins within a least significant bit quantization level is generated, based on the detected difference in arrival time. An M-bit output data is generated based on the comparison signals and the time interpolation signal. A non-uniformity of a code density of the M-bit output data is detected, and based on the detecting the delaying is varied.

    Abstract translation: 将输入信号与2N-1个参考电压进行比较以产生2N-1个对应的二进制值比较信号，延迟比较信号中的至少一个可变延迟并检测延迟信号与另一个比较信号之间的到达时间差。 基于检测到的到达时间的差异，生成对最低有效位量化级内的多个存储体进行编码的时间插值信号。 基于比较信号和时间插值信号生成M位输出数据。 检测到M位输出数据的密度不均匀，并且基于检测延迟变化。

    Analog-to digital converter and analog-to digital conversion apparatus
    45.
    发明授权
    Analog-to digital converter and analog-to digital conversion apparatus 有权
    模数转换器和模数转换装置

    公开(公告)号：US07286072B2

    公开(公告)日：2007-10-23

    申请号：US11354245

    申请日：2006-02-15

    Applicant: Kohji Sakata ,  Seiichi Banba ,  Atsushi Wada

    Inventor： Kohji Sakata ,  Seiichi Banba ,  Atsushi Wada

    IPC: H03M1/12

    CPC classification number: H03M1/007 ,  H03M1/002 ,  H03M1/0809 ,  H03M1/167 ,  H03M1/206 ,  H03M1/365

    Abstract: An analog-to-digital conversion apparatus which has a variable resolution and allows a reduction in power consumption. This apparatus comprises an analog-to-digital converter (ADC) of parallel type, a controller, and an interpolation circuit. The analog-to-digital converter has a plurality of comparators connected in parallel, each for comparing potentials of an analog input signal and a reference signal. The controller generates a control signal for controlling the resolution of the analog-to-digital converter. Specifically, the controller controls the number of comparators (CMP) to operate by means of the control signal, thereby determining the resolution. The interpolation circuit interpolates the output data of the comparators that are disabled depending on the resolution. The controller avoids simultaneous operation of two adjoining comparators when the analog-to-digital converter is operated at a resolution lower than its maximum resolution.

    Abstract translation: 具有可变分辨率并且允许降低功耗的模数转换装置。 该装置包括并行类型的模数转换器（ADC），控制器和内插电路。 模数转换器具有并联连接的多个比较器，每个比较器用于比较模拟输入信号和基准信号的电位。 控制器产生用于控制模数转换器的分辨率的控制信号。 具体地，控制器通过控制信号控制比较器（CMP）的数量来操作，从而确定分辨率。 内插电路根据分辨率插值禁用的比较器的输出数据。 当模数转换器以低于其最大分辨率的分辨率操作时，控制器避免同时操作两个相邻的比较器。

    Response-based analog-to-digital conversion apparatus and method
    48.
    发明授权
    Response-based analog-to-digital conversion apparatus and method 失效
    基于响应的模数转换装置和方法

    公开(公告)号：US06927713B2

    公开(公告)日：2005-08-09

    申请号：US10826239

    申请日：2004-04-16

    Applicant: Donald T. Comer ,  Darren S. Korth

    Inventor： Donald T. Comer ,  Darren S. Korth

    IPC: H03M1/20 ,  H03M1/36

    CPC classification number: H03M1/206 ,  H03M1/365

    Abstract: An apparatus and method for increasing the resolution of analog-to-digital conversion devices and systems is described. The described apparatus and method operate without significantly increasing the complexity or conversion time of conventional analog-to-digital conversion architectures. The improved resolution is accomplished by detecting the time-dependent response characteristics of comparators used within an analog-to-digital converter. The detected response characteristics, such as the response pattern or the response time, are used to estimate the overdrive voltage on the comparator of interest and to thereby provide additional bits to the analog-to-digital conversion process. In those applications where the response characteristics affect the settling characteristics of the converter output bits, additional resolution may be attained by detecting the settling characteristics, such as the settling pattern or settling time, of the converter output bits, particularly the least significant bit.

    Abstract translation: 描述了用于增加模数转换装置和系统的分辨率的装置和方法。 所描述的装置和方法操作而不显着增加常规模数转换架构的复杂性或转换时间。 通过检测在模数转换器内使用的比较器的时间依赖性响应特性来实现改进的分辨率。 检测到的响应特性，例如响应模式或响应时间，用于估计感兴趣的比较器上的过驱动电压，从而为模数转换过程提供额外的位。 在响应特性影响转换器输出位的稳定特性的那些应用中，通过检测转换器输出位，特别是最低有效位的稳定特性，如稳定模式或建立时间，可以获得额外的分辨率。

    A/D conversion method and apparatus
    49.
    发明授权
    A/D conversion method and apparatus 有权
    A / D转换方法和装置

    公开(公告)号：US06879278B2

    公开(公告)日：2005-04-12

    申请号：US10854297

    申请日：2004-05-26

    Applicant: Takamoto Watanabe ,  Takayuki Torigoe ,  Koji Adumi ,  Hidetoshi Yamauchi

    Inventor： Takamoto Watanabe ,  Takayuki Torigoe ,  Koji Adumi ,  Hidetoshi Yamauchi

    IPC: H03K5/135 ,  H03M1/12 ,  H03M1/20 ,  H03M1/50 ,  H03M1/60

    CPC classification number: H03M1/206 ,  G04F10/005 ,  H03M1/502

    Abstract: An A/D converter for driving a plurality of delay units forming a pulse delay circuit by an analog input signal Vin and digitalizing the number of delay units through which a pulse signal passes in the pulse delay circuit at predetermined timings, provided with a plurality of pulse position digitalizing units used for A/D conversion and inputting delay pulses from the delay units of the pulse delay circuit to the pulse position digitalizing units through an inverter group comprised of inverters with different inversion levels (switching threshold level) by different input timings. The digital data obtained by the pulse position digitalizing units are added by an adder.

    Abstract translation: 一种A / D转换器，用于通过模拟输入信号Vin驱动形成脉冲延迟电路的多个延迟单元，并且将预定时间脉冲信号通过脉冲信号的延迟单元的数量化，并设置多个延迟单元 用于A / D转换的脉冲位置数字化单元，并且通过由不同输入定时具有不同反相电平（开关阈值电平）的反相器组成的反相器组将延迟脉冲从脉冲延迟电路的延迟单元输入到脉冲位置数字化单元。 由脉冲位置数字化单元获得的数字数据由加法器相加。

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