公开(公告)号：US4931408A

公开(公告)日：1990-06-05

申请号：US420971

申请日：1989-10-13

申请人： Fwu-Iuan Hshieh

发明人： Fwu-Iuan Hshieh

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66719 ,  H01L29/66712 ,  Y10S148/126 ,  Y10S148/131

摘要： An oxide sidewall spacer is formed on the sidewalls of a gate prior to forming the body region of a DMOS transistor. An ion implantation or diffusion process is then conducted to form the body region, where the gate and the oxide sidewall spacer together act as a mask for self-alignment of the body region. After a drive-in step to diffuse the impurities, the body region will extend only a relatively short distance under the gate due to its initial spacing from the edge of the gate. After the body region is formed, the oxide sidewall spacer is removed, and impurities to form the source region are implanted or diffused into the body region and driven in. Since the extension of the body region under the gate is limited by the oxide sidewall spacer, the channel region between the edge of the source region and the body region under the gate may be made shorter resulting in the channel on-resistance of the transistor being reduced.

公开(公告)号：US4879254A

公开(公告)日：1989-11-07

申请号：US204375

申请日：1988-06-09

申请人： Yukio Tsuzuki ,  Masami Yamaoka

发明人： Yukio Tsuzuki ,  Masami Yamaoka

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/45 ,  H01L29/78

CPC分类号： H01L29/66712 ,  H01L29/7802 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/456 ,  Y10S148/103 ,  Y10S148/111 ,  Y10S148/126 ,  Y10S148/131

摘要： A method for manufacturing a DMOS which comprises forming a first conductive type layer on a substrate, forming a gate oxide layer thereon, forming a gate electrode layer and a second insulating layer successively on the gate oxide layer, forming a second conductive type body region and a first conductive type source region having a narrower width by implanting impurities utilizing the second insulating layer as a mask, forming a side wall spacer of an insulating material on at least a side portion of the gate electrode, forming a conductive passage penetrating the source region and extending into the body region while utilizing the second insulating layer and the side wall spacer as mask, optionally implanting the exposed body region, further excessively etching the sidewall spacer, the masking layer overlying the gate, and the gate oxide prior to providing an electrode connecting the source and body regions.

摘要翻译： 一种DMOS的制造方法，其特征在于，在基板上形成第一导电型层，在其上形成栅极氧化层，在所述栅极氧化层上依次形成栅电极层和第二绝缘层，形成第二导电型体区域， 通过使用第二绝缘层作为掩模注入杂质而具有较窄宽度的第一导电类型源极区域，在栅电极的至少一个侧部分上形成绝缘材料的侧壁隔离物，形成穿透源极区域的导电通路 并且在利用第二绝缘层和侧壁间隔物作为掩模的同时延伸到身体区域中，任选地植入暴露的身体区域，在提供电极之前进一步过度蚀刻侧壁间隔物，覆盖栅极的掩模层和栅极氧化物 连接源和身体区域。

公开(公告)号：US4742379A

公开(公告)日：1988-05-03

申请号：US676359

申请日：1984-11-29

申请人： Yoshimi Yamashita ,  Kinjiro Kosemura ,  Hidetoshi Ishiwari ,  Sumio Yamamoto ,  Shigeru Kuroda

发明人： Yoshimi Yamashita ,  Kinjiro Kosemura ,  Hidetoshi Ishiwari ,  Sumio Yamamoto ,  Shigeru Kuroda

IPC分类号： H01L21/306 ,  H01L21/8236 ,  H01L21/8252 ,  H01L27/06 ,  H01L29/778 ,  H01L29/80

CPC分类号： H01L27/0883 ,  H01L21/30621 ,  H01L21/8236 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/7787 ,  Y10S148/131 ,  Y10S148/168

摘要： A compound semiconductor device comprises an enhancement-mode transistor and a depletion-mode transistor, each of which has a heterojunction and utilizes a two-dimensional electron gas. The method of producing the device comprises the steps of: forming an undoped GaAs channel layer on a semi-insulating GaAs substrate; forming an N-type AlGaAs electron-supply layer so as to form the heterojunction; forming an N-type GaAs layer; forming an AlGaAs layer; selectively etching the AlGaAs layer to form a recess; performing an etching treatment using an etchant which can etch rapidly GaAs and etch slowly AlGaAs to form simultaneously grooves for gate electrodes of the enhancement-mode transistor and the depletion-mode transistor, the bottoms of the grooves being in the N-type AlGaAs layer and the distance between the bottoms being equal to the thickness of the AlGaAs layer; and forming simultaneously the gate electrodes in the grooves.

摘要翻译： 复合半导体器件包括增强型晶体管和耗尽型晶体管，其各自具有异质结并且利用二维电子气。 制造该器件的方法包括以下步骤：在半绝缘GaAs衬底上形成未掺杂的GaAs沟道层; 形成N型AlGaAs电子供给层以形成异质结; 形成N型GaAs层; 形成AlGaAs层; 选择性地蚀刻AlGaAs层以形成凹陷; 使用蚀刻剂进行蚀刻处理，其可以快速蚀刻GaAs并缓慢蚀刻AlGaAs以同时形成用于增强型晶体管和耗尽型晶体管的栅电极的沟槽，凹槽的底部在N型AlGaAs层中，以及 底部之间的距离等于AlGaAs层的厚度; 并且同时在沟槽中形成栅电极。

公开(公告)号：US4742026A

公开(公告)日：1988-05-03

申请号：US42819

申请日：1987-04-27

申请人： Jean Vatus ,  Jean Chevrier

发明人： Jean Vatus ,  Jean Chevrier

IPC分类号： H01L21/306 ,  H01L29/47 ,  H01L21/465

CPC分类号： H01L21/30621 ,  H01L29/475 ,  Y10S148/131

摘要： The invention pertains to a method for the selective etching of a surface layer which is automatically stopped at a subjacent layer.According to the invention, a first layer of a material containing gallium is selectively etched with respect to a second layer containing aluminium by reactive ion etching in the presence of a pure freon plasma C Cl.sub.2 F.sub.2. At low pressures (0.5 to 2.5 pascals), the etching is anisotropic and makes it possible to etch the gate recess of a field effect transistor. At a higher pressure (6 to 10 pascals), the etching is isotropic and makes it possible to sub-etch the first layer.Application to the manufacture of field effect transistors made of group III-V materials, with low access resistances.

摘要翻译： 本发明涉及一种用于选择性蚀刻表面层的方法，该表面层在下层自动停止。 根据本发明，在纯氟利昂等离子体CCl 2 F 2的存在下，通过反应离子蚀刻，相对于含有铝的第二层选择性地蚀刻包含镓的材料的第一层。 在低压（0.5至2.5帕斯卡）时，蚀刻是各向异性的，并且可以蚀刻场效应晶体管的栅极凹槽。 在更高的压力（6至10帕斯卡），蚀刻是各向同性的，并且可以对第一层进行次蚀刻。 应用于制造由III-V族材料制成的场效应晶体管，具有低访问阻抗。

公开(公告)号：US4702000A

公开(公告)日：1987-10-27

申请号：US841297

申请日：1986-03-19

申请人： Dyer A. Matlock ,  Richard L. Lichtel, Jr. ,  Lawrence G. Pearce

发明人： Dyer A. Matlock ,  Richard L. Lichtel, Jr. ,  Lawrence G. Pearce

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/762 ,  H01L21/265 ,  H01L21/22

CPC分类号： H01L29/66575 ,  H01L21/28123 ,  H01L21/762 ,  Y10S148/05 ,  Y10S148/086 ,  Y10S148/122 ,  Y10S148/131 ,  Y10S438/978

摘要： The problem of unwanted residual polysilicon stringers along the sidewalls of a field oxide layer employed in direct moat wafer processing is avoided by a processing scheme in which the sidewalls of the aperture in the field oxide layer are initially tapered prior to formation of the polysilicon layer to be used for the gate electrode(s). Because of the graduated thickness of the sidewalls of the field oxide layer, the thickness of the polysilicon layer formed thereon is substantially uniform over the entirety of the substrate. As a result, during subsequent masking of the polysilicon layer to define the gate electrode(s), all unmasked portions of the polysilicon are completely etched, leaving no residual material (e.g. stringers) that could be a source of device contamination. After the polysilicon gate has been delineated, the sloped sidewalls of the field oxide are removed (by anisotropic etching), so that the sidewalls of the apertures or windows of the field oxide layer will be perpendicular to the planar surface of the substrate, thus facilitating proper formation of dielectric (oxide) spacers therealong, which thereby provide separation between contact materials and the junction created by shallow ion implantation of dopants through the field oxide aperture.

公开(公告)号：US4523372A

公开(公告)日：1985-06-18

申请号：US607868

申请日：1984-05-07

申请人： Raymond J. Balda ,  Yefim Bukhman ,  Willis R. Goodner

发明人： Raymond J. Balda ,  Yefim Bukhman ,  Willis R. Goodner

IPC分类号： H01L21/311 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L21/312

CPC分类号： H01L21/76802 ,  H01L21/31138 ,  Y10S148/131 ,  Y10S438/945 ,  Y10S438/963

摘要： A process is disclosed for fabricating semiconductor devices, and especially for fabricating semiconductor devices having multiple levels of metallization separated by polyimide or other organic materials. The process avoids the sputter etching and redeposition of the lower metal layer during reactive ion etching of openings through the organic layer. Sequential layers overlying the first layer of metallization include a layer of oxide, a layer of organic material, and a second layer of oxide. The second layer of oxide functions as a hard mask for patterning the organic material. The first layer of oxide acts as an etch stop and protective layer to prevent attack of the underlying metal during reactive ion etching of the organic layer. The first layer of oxide is of limited areal extent to avoid subsequent problems with the organic layer. The oxide located at the bottom of the opening through the organic material as well as the second layer of oxide and any oxide which is sputtered and redeposited on the walls of the opening through the organic material are easily removed in a single etch step without adversely affecting the underlying metallization. After removing the oxide, a second layer of metallization is applied and patterned as required.

摘要翻译： 公开了用于制造半导体器件的方法，特别是用于制造具有由聚酰亚胺或其它有机材料分离的多层金属化的半导体器件。 该过程避免了在通过有机层的开口的反应离子蚀刻期间溅射蚀刻和再沉积下部金属层。 覆盖第一层金属化层的顺序层包括一层氧化物，一层有机材料和第二层氧化物层。 第二层氧化物用作图案化有机材料的硬掩模。 第一层氧化物用作蚀刻停止层和保护层，以防止在有机层的反应离子蚀刻期间底层金属的侵蚀。 第一层氧化物的面积有限，以避免有机层的后续问题。 通过有机材料位于开口底部的氧化物以及第二层氧化物和通过有机材料溅射并重新沉积在开口壁上的任何氧化物容易在单个蚀刻步骤中去除而不会不利地影响 底层金属化。 在去除氧化物之后，根据需要施加第二层金属化并图案化。

公开(公告)号：US4341571A

公开(公告)日：1982-07-27

申请号：US201884

申请日：1980-10-29

申请人： Ludwig Hiss ,  Ulrich Waldvogel

发明人： Ludwig Hiss ,  Ulrich Waldvogel

IPC分类号： H01L21/265 ,  H01L21/027 ,  H01L21/26

CPC分类号： H01L21/0274 ,  Y10S148/12 ,  Y10S148/131

摘要： An ion implantation process uses exclusively photoresist masks to cover a substrate except in the regions to be implanted with ions. The photoresist masks are removed after each ion implantation by plasma etching.

摘要翻译： 离子注入工艺仅使用光刻胶掩模来覆盖基板，除了待注入离子的区域之外。 通过等离子体蚀刻在每次离子注入后去除光致抗蚀剂掩模。

公开(公告)号：US4252579A

公开(公告)日：1981-02-24

申请号：US36722

申请日：1979-05-07

申请人： Irving T. Ho ,  Jacob Riseman

发明人： Irving T. Ho ,  Jacob Riseman

IPC分类号： H01L27/10 ,  G11C11/35 ,  G11C11/404 ,  H01L21/31 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78 ,  H01L21/20 ,  H01L21/302

CPC分类号： H01L27/10864 ,  G11C11/35 ,  G11C11/404 ,  H01L21/76229 ,  H01L27/10841 ,  H01L29/7827 ,  Y10S148/05 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S148/117 ,  Y10S148/131

摘要： A method for making highly dense, dielectrically isolated, U-shaped MOSFET. In a preferred method a monocrystalline silicon P substrate with a N+ layer thereon, a P layer on the N+ layer and a N+ layer on the P layer is provided. A pattern of U-shaped openings is formed in the body through to the P substrate by the reactively ion etching technique. This pattern of openings is filled with an insulator material, such as silicon dioxide. A conductive layer of N+ doped polycrystalline silicon is deposited on the bare surface of this silicon body. Openings are formed in the polycrystalline silicon over the silicon dioxide filled openings. A silicon dioxide layer is then grown by, for example, thermal oxidation over the polycrystalline silicon layer. Reactively ion etching is used to produce substantially U-shaped openings through the layers over the P substrate and into the P substrate to substantially bisect the regions of monocrystalline silicon. This etching step forms two storage cells in the monocrystalline silicon areas and a bit line for each column of cells in the polycrystalline silicon layer. A silicon dioxide gate insulator is grownon the monocrystalline silicon surfaces of the U-shaped openings by thermal oxidation in a suitable ambient. Conductively doped polycrystalline silicon is deposited in the U-shaped openings over the silicon dioxide gate insulator layer until the openings are filled and cover the surface of the body. The conductively doped polycrystalline silicon on the surface of the body is etched in a suitable pattern to produce the word lines of the random access memory device.

摘要翻译： 一种用于制造高密度，介电隔离的U形MOSFET的方法。 在优选的方法中，提供了其上具有N +层的单晶硅P衬底，N +层上的P层和P层上的N +层。 通过反应离子蚀刻技术，在体内通过P基板形成U形开口的图案。 这种开口图案填充有诸如二氧化硅的绝缘体材料。 N +掺杂多晶硅的导电层沉积在该硅体的裸露表面上。 在二氧化硅填充的开口上的多晶硅中形成开口。 然后通过例如在多晶硅层上的热氧化来生长二氧化硅层。 反向离子蚀刻用于通过P衬底上的层并且进入P衬底中产生基本上U形的开口，以将单晶硅的区域基本上二等分。 该蚀刻步骤在单晶硅区域中形成两个存储单元，并且在多晶硅层中形成每列单元格的位线。 通过在合适的环境中的热氧化，在U形开口的单晶硅表面上生长二氧化硅栅极绝缘体。 导电掺杂的多晶硅沉积在二氧化硅栅极绝缘体层上的U形开口中，直到开口被填充并覆盖该体的表面。 以合适的图案蚀刻身体表面上的导电掺杂多晶硅，以产生随机存取存储器件的字线。

公开(公告)号：US4159915A

公开(公告)日：1979-07-03

申请号：US844767

申请日：1977-10-25

申请人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  James L. Walsh

发明人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  James L. Walsh

IPC分类号： H01L21/76 ,  H01L21/331 ,  H01L21/74 ,  H01L21/8222 ,  H01L21/8228 ,  H01L27/06 ,  H01L27/07 ,  H01L27/082 ,  H01L29/06 ,  H01L29/417 ,  H01L29/73 ,  H01L29/732 ,  H01L21/265

CPC分类号： H01L29/0649 ,  H01L21/743 ,  H01L21/82285 ,  H01L27/0755 ,  H01L27/0826 ,  H01L27/0828 ,  Y10S148/131

摘要： A method is given for fabricating vertical NPN and PNP structures on the same semiconductor body. The method involves providing a monocrystalline semiconductor substrate having regions of monocrystalline silicon isolated from one another by isolation regions. Buried regions are formed overlapping the juncture of the substrate and epitaxial layer and are located in at least one of the regions of isolated monocrystalline silicon. The P base region in the NPN designated regions and a P reach-through in the PNP designated regions are formed simultaneously. The emitter region in the NPN regions and base contact region in the PNP regions are then formed simultaneously. The P emitter region in the PNP regions is then implanted by suitable ion implantation techniques. A Schottky Barrier collector contact in the PNP regions are formed. Electrical contacts are then made to the PNP and NPN transistor elements. A PNP device may be fabricated without the formation of an NPN device if it is so desired.

摘要翻译： 给出了在同一半导体器件上制造垂直NPN和PNP结构的方法。 该方法包括提供具有通过隔离区彼此隔离的单晶硅区域的单晶半导体衬底。 掩埋区域形成为与衬底和外延层的接合部重叠，并且位于分离的单晶硅的至少一个区域中。 NPN指定区域中的P基区域和PNP指定区域中的P到达通孔同时形成。 然后在NPN区域中的发射极区域和PNP区域中的基极接触区域同时形成。 然后通过合适的离子注入技术注入PNP区域中的P发射极区域。 形成PNP区域中的肖特基势垒集电极触点。 然后对PNP和NPN晶体管元件进行电触点。 如果需要，可以制造PNP器件而不形成NPN器件。

公开(公告)号：US4139442A

公开(公告)日：1979-02-13

申请号：US832856

申请日：1977-09-13

申请人： James A. Bondur ,  Hans B. Pogge

发明人： James A. Bondur ,  Hans B. Pogge

IPC分类号： H01L21/76 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/32 ,  H01L21/762 ,  C23C15/00

CPC分类号： H01L21/308 ,  H01L21/3065 ,  H01L21/32 ,  H01L21/76208 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S148/106 ,  Y10S148/117 ,  Y10S148/131

摘要： A method for producing deeply recessed oxidized regions in silicon. A series of deep trenches are formed in a silicon wafer by a reactive ion etching (RIE) method. In a first species, the trenches are of equal width. A block-off mask is selectively employed during part of the RIE process to produce trenches of unequal depth. The trench walls are thermally oxidized to completely fill in all of the trenches with oxide at the same time. In a second species, the trenches are of equal depth and width and of uniform spacing. In one aspect of the second species, the width of the trenches is equal to the distance between the trenches whereby the thermal oxidation completely fills in the trenches with oxide at the same time that the silicon between the trenches is fully converted to silicon oxide. In another aspect of the second species, the trenches are wider than the distance between the trenches whereby the thermal oxidation only partially fills in the trenches with oxide when the intervening silicon is fully converted to silicon oxide. In the latter aspect, the filling of the trenches is completed by the deposition of suitable material such as pyrolytically deposited silicon oxide.

摘要翻译： 一种在硅中产生深凹陷氧化区的方法。 通过反应离子蚀刻（RIE）法在硅晶片中形成一系列深沟槽。 在第一种物种中，沟槽的宽度相等。 在RIE过程的一部分期间选择性地采用截止掩模以产生不等深度的沟槽。 沟槽壁被氧化，同时完全用氧化物填充到所有的沟槽中。 在第二种物种中，沟槽具有相同的深度和宽度并且具有均匀的间距。 在第二种类的一个方面，沟槽的宽度等于沟槽之间的距离，由此热氧化在氧化物完全填充在沟槽中，同时沟槽之间的硅完全转化为氧化硅。 在第二种类的另一方面，沟槽比沟槽之间的距离宽，由此当中间的硅完全转化为氧化硅时，热氧化仅部分地填充在具有氧化物的沟槽中。 在后一方面，通过沉积合适的材料如热解沉积的氧化硅来完成沟槽的填充。