公开(公告)号：US20170317279A1

公开(公告)日：2017-11-02

申请号：US15352985

申请日：2016-11-16

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Philippe BOIVIN

IPC: H01L45/00

CPC classification number: H01L45/122 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1675

Abstract: A oxide-based direct-access resistive nonvolatile memory may include within the interconnect portion of the integrated circuit a memory plane including capacitive memory cells extending in orthogonal first and second directions and each including a first electrode, a dielectric region and a second electrode. The memory plane may include conductive pads of square or rectangular shape forming the first electrodes. The stack of the dielectric layer and the second conductive layer covers the pads in the first direction and forms, in the second direction, conductive bands extending over and between the pads. The second electrodes may be formed by zones of the second bands facing the pads.

公开(公告)号：US20170309532A1

公开(公告)日：2017-10-26

申请号：US15648135

申请日：2017-07-12

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero

IPC: H01L23/04 ,  B81B3/00 ,  H01L49/02 ,  H01L23/522 ,  H01G5/18 ,  H01L27/06

CPC classification number: H01L23/04 ,  B81B3/0021 ,  B81B2201/0221 ,  H01G5/18 ,  H01L23/5223 ,  H01L27/0629 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes several metallization levels separated by an insulating region. A hollow housing whose walls comprise metallic portions is produced within various metallization levels. A controllable capacitive device includes a suspended metallic structure situated in the hollow housing within a first metallization level including a first element fixed on two fixing zones of the housing and at least one second element extending in cantilever fashion from the first element and includes a first electrode of the capacitive device. A second electrode includes a first fixed body situated at a second metallization level adjacent to the first metallization level facing the first electrode. The first element is controllable in flexion from a control zone of this first element so as to modify the distance between the two electrodes.

公开(公告)号：US09801070B2

公开(公告)日：2017-10-24

申请号：US14850676

申请日：2015-09-10

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Charles

IPC: H04W12/02 ,  H04W12/08 ,  G06Q20/32 ,  H04M1/725 ,  H04W4/00 ,  H04W12/06 ,  H04M1/67

CPC classification number: H04W12/08 ,  G06Q20/3227 ,  G06Q20/3229 ,  H04M1/67 ,  H04M1/7253 ,  H04M2250/04 ,  H04W4/80 ,  H04W12/06

Abstract: A method and a device for protecting a security module connected to a near-field communication router in a telecommunication device, wherein a transmission between the router and the security module is only allowed in the presence of a radio frequency communication flow detected by the router.

公开(公告)号：US20170302168A1

公开(公告)日：2017-10-19

申请号：US15363631

申请日：2016-11-29

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Paola Cavaleri

IPC: H02M3/07

CPC classification number: H02M3/07 ,  G11C5/145 ,  G11C16/30

Abstract: A charge pump circuit can be controlled by a control signal that is generated from a first signal coming from and output signal of the charge pump circuit, from a reference signal, and from a clock signal. The generation of the control signal includes a comparison of the reference signal and of the first signal in tempo with a timing signal coming from the clock signal.

公开(公告)号：US20170286687A1

公开(公告)日：2017-10-05

申请号：US15622991

申请日：2017-06-14

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Yannick Teglia

IPC: G06F21/57 ,  G01K13/00 ,  G06F21/71 ,  G06F21/55 ,  G06F12/14

CPC classification number: G06F21/575 ,  G01K13/00 ,  G06F12/1458 ,  G06F21/554 ,  G06F21/71 ,  G06F2212/1052 ,  G06F2221/034 ,  G06F2221/2137

Abstract: A method of detecting a cold-boot attack includes transferring, into a first volatile memory of an integrated circuit, a pattern stored in a non-volatile memory of the integrated circuit. Power to the non-volatile memory is periodically interrupted and an indication of a number of errors in the non-volatile memory is generated. The indication of the number of errors is compared to one or more thresholds. An occurrence of a cold-boot attack is detected based on the comparison. The pattern may be reloaded into the first volatile memory before each power interruption. The pattern may be selected so that the number of errors varies according to the integrated circuit temperature.

公开(公告)号：US09780098B2

公开(公告)日：2017-10-03

申请号：US15229709

申请日：2016-08-05

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Marc Battista ,  François Tailliet

IPC: H01L27/11 ,  G11C11/412 ,  G11C11/418 ,  G11C16/04 ,  G11C16/08 ,  H01L27/088 ,  H01L29/49 ,  H01L29/51 ,  G11C14/00 ,  H01L21/8234

CPC classification number: H01L27/1104 ,  G11C11/4125 ,  G11C11/418 ,  G11C14/0063 ,  G11C16/045 ,  G11C16/08 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/4916 ,  H01L29/513

Abstract: An integrated structure includes a first MOS transistor with a first controllable gate region overlying a first gate dielectric and a second MOS transistor neighboring the first MOS transistor and having a second controllable gate region overlying the first gate dielectric. A common conductive region overlies the first and second gate regions and is separated therefrom by a second gate dielectric. The common conductive region includes a continuous element located over a portion of the first and second gate regions and a branch extending downward from the continuous element toward the substrate as far as the first gate dielectric. The branch located between the first and second gate regions.

公开(公告)号：US09767277B2

公开(公告)日：2017-09-19

申请号：US15405044

申请日：2017-01-12

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Yannick Teglia

IPC: G06G7/58 ,  G06F21/55 ,  G06F7/58

CPC classification number: G06F21/55 ,  G06F7/58 ,  G06F21/556

Abstract: A method for detecting a fault injection in a circuit, wherein a bit pattern is mixed in a bit stream originating from a noise source and the presence of this pattern is detected in a signal sampled downstream of the mixing.

公开(公告)号：US20170263320A1

公开(公告)日：2017-09-14

申请号：US15608770

申请日：2017-05-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/34 ,  G11C16/26 ,  G11C16/12

CPC classification number: G11C16/102 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/12 ,  G11C16/26 ,  G11C16/3481 ,  G11C16/3495 ,  G11C2211/5622 ,  G11C2211/5624 ,  G11C2211/5632

Abstract: During a phase of programming the cell, a first voltage is applied to the source region and a second voltage, higher than the first voltage, is applied to the drain region until the cell is put into conduction. The numerical value of the item of data to be written is controlled by the level of the control voltage applied to the control gate and the item of data is de facto written with the numerical value during the putting into conduction of the cell. The programming is then stopped.

公开(公告)号：US20170178733A1

公开(公告)日：2017-06-22

申请号：US15453663

申请日：2017-03-08

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco LA ROSA ,  Stephan NIEL ,  Arnaud REGNIER

IPC: G11C16/26 ,  G11C16/08 ,  H01L23/528 ,  H01L23/535 ,  H01L23/522 ,  H01L29/423 ,  G11C16/04 ,  H01L27/11556

CPC classification number: G11C16/26 ,  G11C7/18 ,  G11C16/0408 ,  G11C16/0433 ,  G11C16/08 ,  H01L21/76816 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/42324

Abstract: Non-volatile memory including rows and columns of memory cells, the columns of memory cells including pairs of twin memory cells including a common selection gate. According to the disclosure, two bitlines are provided per column of memory cells. The adjacent twin memory cells of the same column are not connected to the same bitline while the adjacent non-twin memory cells of the same column are connected to the same bitline.

公开(公告)号：US09666484B2

公开(公告)日：2017-05-30

申请号：US14806432

申请日：2015-07-22

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Arnaud Regnier ,  Stephan Niel ,  Francesco La Rosa

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/49 ,  H01L21/265 ,  H01L27/108 ,  H01L27/1157 ,  H01L29/772 ,  H01L21/28 ,  H01L29/423 ,  H01L29/788 ,  H01L27/11524 ,  H01L27/11556

CPC classification number: H01L21/823468 ,  H01L21/26513 ,  H01L21/28273 ,  H01L21/823425 ,  H01L21/823443 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/4236 ,  H01L29/4975 ,  H01L29/6656 ,  H01L29/66613 ,  H01L29/66825 ,  H01L29/772 ,  H01L29/7881

Abstract: An integrated circuit is formed on a semiconductor substrate and includes a trench conductor and a first transistor formed on the surface of the substrate. The transistor includes: a transistor gate structure, a first doped region extending in the substrate between a first edge of the gate structure and an upper edge of the trench conductor, and a first spacer formed on the first edge of the gate structure and above the first doped region. The first spacer completely covers the first doped region and a silicide is present on the trench conductor but is not present on the surface of the first doped region.